Power Efficient Approximate Booth Multiplier

Venkatachalam, S.; Lee, Hyuk Jae; Ko, Seok‐Bum

doi:10.1109/iscas.2018.8351708

Cited by 27 publications

(7 citation statements)

References 13 publications

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“…The studies most related to the work performed here, employing non-digitized bitserial polynomial multiplication methods, include [1,3,4,[12][13][14][15][16][17]. These hardware accelerators are implemented on field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) platforms.…”

Section: Related Hardware Accelerators and Limitationsmentioning

confidence: 99%

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A Flexible Hardware Accelerator for Booth Polynomial Multiplier

Sonbul

2024

Applied Sciences

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This article presents a parameterized/flexible hardware accelerator design tailored for the Booth polynomial multiplication method. The flexibility is achieved by allowing users to compute multiplication operations across various operand lengths, reaching up to 212 or 4096 bits. Our optimization strategy involves resource reuse, effectively minimizing the overall area cost of the Booth accelerator design. A comprehensive evaluation compares the proposed multiplier design with several non-digitized bit-serial polynomial multiplication accelerators. Implementation is realized in Verilog HDL using the Vivado IDE tool, featuring diverse operand sizes, and post-place and route assessments are performed on the Xilinx Virtex-7 field-programmable gate array device. For the largest considered operand size of 1024 × 1024, our Booth accelerator utilizes 1434 slices and can operate on a maximum frequency of 523.56 MHz. A single polynomial multiplication operation requires 0.977 μs and the total power consumption is 927 mW. Moreover, a comparison to state-of-the-art accelerators reveals that the proposed flexible accelerator is 1.34× faster in computation time and 1.05× more area-efficient than the recent dedicated polynomial multiplication design. Therefore, the implementation results and comparison to the state of the art show that the proposed accelerator is suitable for a wide range of cryptographic applications.

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Section: Related Hardware Accelerators and Limitationsmentioning

confidence: 99%

“…The architectures of Booth polynomial multipliers are considered in [15][16][17]. In [15,18], a radix-4 Booth multiplier accelerator is presented where the authors use an approximation technique to generate the partial products.…”

Section: Related Hardware Accelerators and Limitationsmentioning

confidence: 99%

A Flexible Hardware Accelerator for Booth Polynomial Multiplier

Sonbul

2024

Applied Sciences

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“…Wallace Tree Adder structures have been used to sum the partial products in reduced time. The aim of ours is to minimize the computation time by using booth algorithm [2]for multiplication. It is totally comprised of concealing the partial products and multiplier bits.…”

Section: Modified Booth Multiplier Designmentioning

confidence: 99%

“…The accumulation of the partial products is improved by the Wallace tree. The speed, area and power consumption [2] of the multipliers will be in direct proportion to the efficiency of the Accumulation rate.…”

Section: Modified Booth Multiplier Designmentioning

confidence: 99%

FFT Implementation using Modified Booth Multiplier and CLA

Joseph,

Shyam,

Mathiazhagan

et al. 2020

IJEAT

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In the field of digital signal and image processing the Fast Fourier Transform (FFT) is one of the rudimentary operations. Telecommunication, Automotive, Hearing devices, Voice recognition systems are some of the applications of Fast Fourier Transform. DFT is implemented using FFT which is a type of algorithm that computes DFT in a fast and efficient manner. This project concentrates on the development of the Fast Fourier Transform (FFT), based on Decimation In Time (DIT) domain, Radix2 algorithm, using VHDL as a design entity.The objective of this project is to establish an efficient design that computes FFT in a faster way. In this project FFT is implemented using modified booth multiplier and CLA and simulated on Xilinx ISE.

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“…Adaptable multipliers with flexibility in switching between exact and approximate modes are proposed using Dual mode compressor [26], variable approximation mode compressor with error recovery, and ultra-low power compressor [27]. A high-speed multiplier employing reduced critical path node capacitance approximate compressor is proposed in [28][29][30][31]. In [32], a probabilistic based approach for PP accumulation based on significant bit position is proposed to minimize logic complexity and power dissipation.…”

Section: Introductionmentioning

confidence: 99%

Design of Precise Multiplier Using Inexact Compressor for Digital Signal Processing

Shanmugam¹,

Natarajan²,

Sundaram³

et al. 2022

Computer Systems Science and Engineering

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In the recent years, error recovery circuits in optimized data path units are adopted with approximate computing methodology. In this paper the novel multipliers have effective utilization in the newly proposed two different 4:2 approximate compressors that generate Error free Sum (ES) and Error free Carry (EC). Proposed ES and Proposed EC in 4:2 compressors are used for performing Partial Product (PP) compression. The structural arrangement utilizes Dadda structure based PP. Due to the regularity of PP arrangement Dadda multiplier is chosen for compressor implementation that favors easy standard cell ASIC design. In this, the proposed compression idealogy are more effective in the smallest n columns, and the accurate compressor in the remaining most significant columns. This limits the error in the multiplier output to be not more than 2 n for an n X n multiplication. The choice among the proposed compressors is decided based on the significance of the sum and carry signals on the multiplier result. As an enhancement to the proposed multiplier, we introduce two Area Efficient (AE) variants viz., Proposed-AE (P-AE), and P-AE with Error Recovery (P-AEER). The proposed basic P-AE, and P-AEER designs exhibit 46.7%, 52.9%, and 52.7% PDP reduction respectively when compared to an approximate multiplier of minimal error type and are designed with 90nm ASIC technology. The proposed design and their performance validation are done by using Cadence Encounter. The performance evaluations are carried out using cadence encounter with 90nm ASIC technology. The proposed-basic P-AEA and P-AEER designs demonstrate 46.7%, 52.9% and 52.7% PDP reduction compared to the minimal error approximate multiplier. The proposed multiplier is implemented in digital image processing which revealed 0.9810 Structural SIMilarity Index (SSIM), to the least, and less than 3% deviation in ECG signal processing application.

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Power Efficient Approximate Booth Multiplier

Cited by 27 publications

References 13 publications

A Flexible Hardware Accelerator for Booth Polynomial Multiplier

A Flexible Hardware Accelerator for Booth Polynomial Multiplier

FFT Implementation using Modified Booth Multiplier and CLA

Design of Precise Multiplier Using Inexact Compressor for Digital Signal Processing

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