Power efficient error correction coding for on‐chip interconnection links

Velayudham, Sumitra; Rajagopal, Sivakumar; Rao, Y. V. Ramana; Ko, Seok‐Bum

doi:10.1049/iet-cdt.2019.0082

Cited by 5 publications

(2 citation statements)

References 47 publications

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“…In Velayudham et al [20] a self-calibrated error correction code was introduced which can correct all single-bit random and up to five bits of burst error imparting probability of 100% error correction along with prevention of crosstalk. The code was equipped with standard triple error correction methods and also employed facility of single and double error detection by using extended hamming code defined as (22,16).…”

Section: Literature Surveymentioning

confidence: 99%

“…The majority of estimated circuits are designed to allow for a trade-off between power consumption and accuracy and energy; however, optimizing one would place limitations on the other [19]. According to [20] Error correction and detection were not performed at various stages of the communication stack. Similarly, in [21,23] the coding scheme was ineffective because of its error-correcting capabilities and presence of crosstalk.…”

Section: Literature Surveymentioning

confidence: 99%

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Prediction of Intermittent Failure by Presage Debacle Model in Network on Chip

Singh¹,

Ravindra²,

Naik³

2022

IJCNIS

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With the emergence of deep sub-micron technology, the reliability issues in on-chip interconnect has enormously increased. This includes single event upsets, like soft errors, and hard faults which are rapidly becoming important factors to be considered. Aggressive technology scaling renders these architectures vulnerable to system performance, intermittent failure, capacitive crosstalk, and power dissipation problem. To improve the performance of the area and power consumption along with bandwidth, throughput and latency, a Buffer Potency Power Gating Technique is carried out to predict the Intermittent Failure by Presage Debacle Model in Network on Chip. In the Presage Debacle Model, the links present in the application-specific topology are provided with real application traffic to assist in prediction of the intermittent failure. By predicting the failure, the output of the model provides the power dissipated over the connection of the application link. Then the crosstalk noise in the topology is reduced by the Adaption of Simulated Annealing (SA) based Particle Swarm Optimization (PSO) congruence algorithm. The optimization congruence algorithm assigns each task in the application software to each node in the topology to determine the network's optimal output. It continuously changes the task park position in the topology system and reduces the crosstalk of the NoC. Consecutively, the area and power consumption are minimized by Buffer Potency Power Gating Technique. Buffer efficiency is increased and the power-gating is a practical way to mitigate NoC power control schemes properly and effectively without any loss in performance. Thus the prediction of intermittent failure is obtained by utilizing NoC to improve the performance of area and power consumption.

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Section: Literature Surveymentioning

confidence: 99%