Power-Efficient Explicit-Pulsed Dual-Edge Triggered Sense-Amplifier Flip-Flops

Abstract

A novel explicit-pulsed dual-edge triggered sense-amplifier flip-flop (DET-SAFF) for low-power and high-performance applications is presented in this paper. By incorporating the dual-edge triggering mechanism in the new fast latch and employing conditional precharging, the DET-SAFF is able to achieve low-power consumption that has small delay. To further reduce the power consumption at low switching activities, a clock-gated sense-amplifier (CG-SAFF) is engaged. Extensive post-layout simulations proved that the proposed DET-SAFF exhibits both the low-power and high-speed properties, with delay and power reduction of up to 43.3% and 33.5% of those of the prior art, respectively. When the switching activity is less than 0.5, the proposed CG-SAFF demonstrates its superiority in terms of power reduction. During zero input switching activity, CG-SAFF can realize up to 86% in power saving. Lastly, a modification to the proposed circuit has led to an improved common-mode rejection ratio (CMRR) DET-SAFF.

A novel low power and high speed double edge explicit pulse triggered level converter flip‐flop

“…The simulation results were obtained from HSPICE (Synopsys, USA). The setup time, which is optimum data to clock delay that leads to data to output delay, equals minimum data to output delay [13,14]. VDDH was 1.1 V, and the best power consumption was obtained when the VDDL to VDDH ratio was 0.6 or 0.7; so, VDDL was considered 0.8 V. Figure 6 shows the simulation setup used in this paper.…”

“…Another parameter was holding time, which is clock to data delay that leads to 5% increment of clock to output delay with respect to minimum clock to output delay [13]. The setup time, which is optimum data to clock delay that leads to data to output delay, equals minimum data to output delay [13,14]. The proposed flip-flop had negative setup time.…”

Low Power High-Efficiency Shift Register Using Implicit Pulse-Triggered Flip-Flop in 130 nm CMOS Process for a Cryptographic RFID Tag

“…In the current trend of CMOS technology, low power consumption is considered as the most important factor, especially for handheld applications and portable devices. The clock system power consumption is estimated as the half of the overall system power [13][14][15]. Therefore, the FFs contribute a substantial percentage of the chip area and power In order to design an efficient shift register, few crucial performance parameters must be taken into consideration, such as power dissipation, area, delay, and leakage [8,9].…”

“…The clock system power consumption is estimated as the half of the overall system power [13][14][15]. Therefore, the FFs contribute a substantial percentage of the chip area and power consumption in the whole system [16,17].…”

Power Efficient Dual Edge-Triggered Storage Design

“…By using dual-edge triggered flip-flops (DETFFs), the clock frequency can be significantly reduced-ideally, cut in half-while preserving the rate of data processing [11]. In many digital VLSI designs, the clock system that includes clock distribution network and flip-flops is one of the highest power consuming components and accounts for 30% to 60% of the total system power, out of which 90% is consumed by the flip-flops and the last branches of the clock distribution network that are driving the flip-flops [12]. So using lower clock frequency may translate into considerable power savings.…”