Power‐gating technique for network‐on‐chip buffers

Casu, Mario R.; Yadav, Manoj Kumar; Zamboni, Maurizio

doi:10.1049/el.2013.3225

Cited by 14 publications

(8 citation statements)

References 5 publications

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“…However, due to the implementation overhead, the final solution is to split each buffer in two parts: an always-on part with a few slots, able to handle low traffic demands, and a larger second buffer that is switched on when the number of flits stored in the always-on part of the buffer exceed a certain threshold. A similar solution with double-threshold control has been proposed by Casu et al in [4], achieving zero performance penalties. On the other hand, BalckOut does not require any modifications to the buffer architecture of the NoC router.…”

Section: Fine-grained Power Gatingmentioning

confidence: 92%

BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers

Zoni

Canidio

Fornaciari

et al. 2017

Journal of Parallel and Distributed Computing

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Section: Fine-grained Power Gatingmentioning

confidence: 92%

BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers

Zoni

Canidio

Fornaciari

et al. 2017

Journal of Parallel and Distributed Computing

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“…Several recent studies have adopted power-gating technique in NoC design. Since router buffers consume the largest portion of the NoC's leakage power, power-gating is utilized to reduce buffer leakage power in [10]. Instead of turning the whole buffer off, it keeps partial buffer active to store incoming flits at all times and then avoids negative performance affection.…”

Section: Related Work and Motivationmentioning

confidence: 99%

“…else if Sliced router is fully-on then (10) if (21) if ( the sliced router is fully on. For the convenience of description, we use the abbreviation UniMesh/UniTorus to indicate the ever-on subnet in the sliced mesh/torus when all gated slices are deactivated.…”

Section: Journal Of Electrical and Computer Engineeringmentioning

confidence: 99%

Applying Partial Power-Gating to Direction-Sliced Network-on-Chip

Wang

Tang

Zhang

2015

Journal of Electrical and Computer Engineering

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Network-on-Chip (NoC) is one of critical communication architectures for future many-core systems. As technology is continually scaling down, on-chip network meets the increasing leakage power crisis. As a leakage power mitigation technique, power-gating can be utilized in on-chip network to solve the crisis. However, the network performance is severely affected by the disconnection in the conventional power-gated NoC. In this paper, we propose a novel partial power-gating approach to improve the performance in the power-gated NoC. The approach mainly involves a direction-slicing scheme, an improved routing algorithm, and a deadlock recovery mechanism. In the synthetic traffic simulation, the proposed design shows favorable power-efficiency at low-load range and achieves better performance than the conventional power-gated one. For the application trace simulation, the design in the mesh/torus network consumes 15.2%/18.9% more power on average, whereas it can averagely obtain 45.0%/28.7% performance improvement compared with the conventional power-gated design. On balance, the proposed design with partial power-gating has a better tradeoff between performance and power-efficiency.

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“…Therefore, the optimal approach is using hybrid buffer/bufferless ports with bypass paths in order to provide efficient NoC architectures. [35][36][37][38][39][40][41][42][43] In this article, we propose HiFMP, a high-performance FPGA-based NoC router that provides low latency, low power consumption, and moderate low area. The structure of HiFMP is simple, fine-grain, modular with low hardware usage and it employs several techniques for using the benefits of FPGA devices and for effectively reducing power consumption.…”

mentioning

confidence: 99%

A high‐performance FPGA‐based multicrossbar prioritized network‐on‐chip

Alaei

Yazdanpanah

2020

Concurrency and Computation

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High performance system-on-chip (SoCs) designs have led to high-density integrated circuits using field programmable gate arrays (FPGAs) for rapid prototyping and reconfigurable digital circuits. Using FPGA reconfigurability, it is possible to design a configurable network-on-chip (NoC) for different applications. NoC architectures provide efficient communication infrastructures for implementing very large SoCs. In this article, we propose HiFMP, a high-performance FPGA-based multicrossbar prioritized NoC router. The aim followed by the proposed router is designing a low-power NoC router with high performance in terms of energy-efficiency, network throughput, area, and latency for efficient FPGA realization. HiFMP is a parameterizable router, and is effectively used for an FPGA-based NoC with mesh topology. Performance evaluations include network-level analysis and hardware exploration; the results demonstrate the effectiveness and high performance of HiFMP in terms of latency, throughput, power consumption, and area, comparing with the existing related architectures. K E Y W O R D S FPGA, low-power design, multicrossbar, network-on-chip, priority-based router 1 INTRODUCTION In high-density emerging SoC architectures, there are a large number of processing elements (PEs) communicating through intensive on-chip interconnections that significantly affect different aspects of the performance. For large SoCs, point-to-point and bus-based interconnections do not provide efficient on-chip network infrastructures because of large amount of hardware, high latency, high power consumption, and/or complicated synchronization. NoCs, as high-performance architectures, arise to overcome the limitations of traditional on-chip structures. 1-5 NoCs provide high-performance and power scalable and modular interconnections. In addition, with NoC architectures, the system complexity is reduced by separating communication and computation units. A NoC includes routers, links, and network interfaces in order to prepare a network infrastructure for interconnecting PEs. Links of NoCs consist of physical channels (i.e., a group of wires), and optional virtual channels (VCs) as a set of additional buffers in routers. 4-7 The channel bit-width (the number of wires in a unidirectional channel) depends on the bandwidth requirements of the applications and available chip area. Generally, links of NoC have two physical unidirectional channels for fully duplexed communication, allowing data to flow both ways without collisions. 1 Routers are the most important modules of the communication backbone of NoC architectures. So, it is essential to design them with low latency, low power consumption, and high throughput. The router complexity and performance impacts the latency, power consumption, area, throughput, and the cost of on-chip networks. 8 Field programmable gate arrays (FPGAs) are flexible, easy-to-use, and cost effective reprogrammable devices with fast and simple design flow. FPGA designers generally do not need to care for clock distribut...

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Power‐gating technique for network‐on‐chip buffers

Cited by 14 publications

References 5 publications

BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers

BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers

Applying Partial Power-Gating to Direction-Sliced Network-on-Chip

A high‐performance FPGA‐based multicrossbar prioritized network‐on‐chip

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