A great interest has been gained in recent years by a new error-correcting code technique, known as "turbo coding," which has been proven to offer performance closer to the Shannon's limit than traditional concatenated codes. In this paper, several very large scale integration (VLSI) architectures suitable for turbo decoder implementation are proposed and compared in terms of complexity and performance; the impact on the VLSI complexity of system parameters like the state number, number of iterations, and code rate are evaluated for the different solutions. The results of this architectural study have then been exploited for the design of a specific decoder, implementing a serial concatenation scheme with 2/3 and 3/4 codes; the designed circuit occupies 35 mm 2 , supports a 2-Mb/s data rate, and for a bit error probability of 10 06 , yields a coding gain larger than 7 dB, with ten iterations.

The International Technology Roadmap of Semiconductors suggests that Quantum Dot Cellular Automata technology might be a possible CMOS substitute. In particular, Magnetic Quantum Dot Cellular Automata (MQCA) have recently drawn the attention of the researchers. Previous experimental works have demonstrated that MQCA are feasible, and can be fabricated with existing technological processes. They are also attractive due to their compactness and to an extremely small power dissipation. Unlike in previous contributions, where architectural blocks are often presented without or only slightly considering their relations with technology, here we conceived, implemented and described a complex MQCA computational block maintaining a clear link with technology. This link is achieved at different levels. At an architectural level we propose the use of delay insensitive Null Convention Logic T M (NCL, [1]). It is implemented for magnetic QCA in order to solve the "layout=timing" problem in the specific case of Magnetic QCA. We thus describe an architectural block at system level using a Hardware Description Language (HDL). This NCL-HDL idea is adapted to a new structure, which we have called "snake-clock", proposed as a feasible solution for the problem of clock delivery, essential for MQCA operations. Furthermore we demonstrated by means of accurate micromagnetic and finite element method simulations that the three-phase "snake-clock" NCL structure works correctly.

A better physiological and productive performance of cv. Montepulciano versus cv. Sangiovese under well-watered conditions has been recently assessed. The objective of this study was to verify that this behaviour is maintained when a pre-veraison deficit irrigation (vines held at 40% pot capacity from fruit-set to veraison) followed by re-watering (pot capacity reported at 90%). Single leaf assimilation rate and stomatal conductance, diurnal and seasonal whole-canopy net CO2 exchange (NCER) and water use efficiency were always higher in Sangiovese under deficit irrigation. Due to water shortage Montepulciano displayed a more compact growing habit due to decreased shoot and internode length. Sangiovese showed excellent recovery upon re-watering as NCER resulted to be higher than the pre-stress period; however, this might also relate to early and severe basal leaf yellowing and shedding. Early deficit irrigation affected xylem characteristics of Montepulciano more than in Sangiovese; vessel density increased (37 vs 29%, respectively, compared with well-watered vines) and the hydraulic conductance decreased more (–13 vs –3% respectively) compared with well-watered vines. Yield components and technological maturity were similar in the two cultivars, whereas Montepulciano grapes had lower anthocyanins and phenolics. Higher physiological and productive efficiency under non-limiting water conditions showed by Montepulciano compared with Sangiovese was basically reversed when both cultivars were subjected to an early deficit irrigation.

The recently proposed NanoMagnet based Logic (NML) represents an innovative way to assemble electronic logic circuits. The low power consumption, combined with the possibility to maintain the information stored without power supply, allows to design low power digital circuits far beyond the limitations of CMOS technology. This work is focused on the key logic block of NanoMagnet based Logic, the Majority Voter (MV). It is thoroughly analyzed through detailed micromagnetic simulations, changing the geometrical parameters, and detecting logic behavior, timing performance and energy dissipation. Our analysis enables to derive important results, substantially enhancing the practical knowledge of NML. First, we demonstrate that NML circuits can be effectively fabricated not only using Electron Beam Lithography, but also using high-end optical lithography without loosing performance. This is a promising opportunity for the future of this technology. Second, we demonstrate the robustness of the MV considering process variations and extracting useful guidelines for its technological implementation. Third, we show how, and how much, the alteration of magnets sizes and distances affect timing and energy consumption. Finally, fourth, we outline the problematic fabrication of the gate with real clock wires, and propose a modification that enables the fabrication of working gates, remarkably enhancing the possibilities of this technology.

In recent years, magnetic-based technologies, like nanomagnet logic (NML), are gaining increasing interest as possible substitutes of CMOS transistors. The possibility to mix logic and memory in the same device, coupled with a potential low power consumption, opens up completely new ways of developing circuits. The major issue of this technology is the necessity to use an external magnetic field as clock signal to drive the information through the circuit. The power losses due to the magnetic field generation potentially wipe out any advantages of NML. To solve this problem, new clock mechanisms were developed, based on spin transfer torque current and on voltage-controlled multiferroic structures that use magnetoelastic properties of magnetic materials, i.e., exploiting the possibility of influencing magnetization dynamics by means of the elastic tensor. In particular, the latter shows an extremely low power consumption. In this paper, we propose an innovative voltage-controlled magnetoelastic clock system aware of the technological constraints risen by modern fabrication processes. We show how circuits can be fabricated taking into account technological limitations, and we evaluate the performance of the proposed system. Results show that the proposed solution promises remarkable improvements over other NML approaches, even though state-of-the-art ideal multiferroic logic has in theory better performance. Moreover, since the proposed approach is technology-friendly, it gives a substantial contribution toward the fabrication of a full magnetic circuit and represents an optimal tradeoff between performance and feasibility