Power management in the Intel Xeon E5 v3

Varma, Ankush; Bowhill, Bill; Crop, Jason; Gough, Corey; Griffith, Brian J; Kingsley, Dan; Sistla, Krishna

doi:10.1109/islped.2015.7273542

Cited by 14 publications

(8 citation statements)

References 2 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Many existing works investigate the potential of integrated VRs [21,67,75,125,127,137]. PowerSoC [127] is an analytical model of a PDN system that includes on-chip VRs, o -chip VRs, and PDN models, providing a platform to evaluate performance and explore the design space of the entire PDN system.…”

Section: Related Workmentioning

confidence: 99%

FlexWatts: A Power- and Workload-Aware Hybrid Power Delivery Network for Energy-Efficient Microprocessors

Haj-Yahya¹,

Alser²,

Kim³

et al. 2020

Preprint

View full text Add to dashboard Cite

Modern client processors typically use one of three commonlyused power delivery network (PDN) architectures: 1) motherboard voltage regulators (MBVR), 2) integrated voltage regulators (IVR), and 3) low dropout voltage regulators (LDO). We observe that the energy-e ciency of each of these PDNs varies with the processor power (e.g., thermal design power (TDP) and dynamic power-state) and workload characteristics (e.g., workload type and computational intensity). This leads to energyine ciency and performance loss, as modern client processors operate across a wide spectrum of power consumption and execute a wide variety of workloads.To address this ine ciency, we propose FlexWatts, a hybrid adaptive PDN for modern client processors whose goal is to provide high energy-e ciency across the processor's wide range of power consumption and workloads. FlexWatts provides high energy-e ciency by intelligently and dynamically allocating PDNs to processor domains depending on the processor's power consumption and workload. FlexWatts is based on three key ideas. First, FlexWatts combines IVRs and LDOs in a novel way to share multiple on-chip and o -chip resources and thus reduce cost, as well as board and die area overheads. This hybrid PDN is allocated for processor domains with a wide power consumption range (e.g., CPU cores and graphics engines) and it dynamically switches between two modes: IVR-Mode and LDO-Mode, depending on the power consumption. Second, for all other processor domains (that have a low and narrow power range, e.g., the IO domain), FlexWatts statically allocates o -chip VRs, which have high energy-e ciency for low and narrow power ranges. Third, FlexWatts introduces a novel prediction algorithm that automatically switches the hybrid PDN to the mode (IVR-Mode or LDO-Mode) that is the most bene cial based on processor power consumption and workload characteristics.

show abstract

Section: Related Workmentioning

confidence: 99%

FlexWatts: A Power- and Workload-Aware Hybrid Power Delivery Network for Energy-Efficient Microprocessors

Haj-Yahya¹,

Alser²,

Kim³

et al. 2020

Preprint

View full text Add to dashboard Cite

show abstract

“…They discovered that hybrid architectures with both on-chip and off-chip VRs can achieve a better tradeoff between area reduction and efficiency requirements compared to traditional off-chip paradigms. In addition, previous works [1]- [4] claimed that the fully integrated voltage regulator (FIVR) that was first adopted at Intel® 4th [1] processor is raising the performance and increases battery-life. Haoran et al [24] compared the characteristics of different power delivery for many cores system using on-chip and/or off-chip VRs based on an analytical model.…”

Section: Related Workmentioning

confidence: 99%

“…Motivation: Previous studies [1]- [4] claimed that the adoption of IVR increases both battery-life and performance (such as at Intel ® 4th generation Core™ microprocessors code name Haswell [1]), but to the best of our knowledge, there is no comprehensive study that evaluated the tradeoffs of IVR across various microprocessors' TDP and workload scenarios. This forms the motivation of this work.…”

Section: Introductionmentioning

confidence: 99%

A Comprehensive Evaluation of Power Delivery Schemes for Modern Microprocessors

Haj-Yahya

Rotem

Mendelson

et al. 2019

20th International Symposium on Quality Electronic Design (ISQED)

View full text Add to dashboard Cite

The continuous quest for energy-efficient computing has led towards the adoption of fine-grained controls in processor sub-systems, of which power delivery network is the most prominent one. Recent industry trends reflect a shift towards on-chip, integrated voltage regulator (IVRs) to that effect. We undertake a thorough and quantitative evaluation of different power delivery networks for modern microprocessors. In contrast to the current trend, we conclude that IVR schemes perform worse compared to the conventional off-chip voltage regulator scheme. Further, we present studies on diverse workloads and Thermal Design Points (TDPs) to highlight the importance of workload-specific power delivery scheme. To the best of our knowledge, this is the first comprehensive study across processors' TDPs and workloads.

show abstract

“…Cloud computing in data-centers, internet-of-things devices, as well as applications related to mobile communication, automotive, and artificial intelligence drive the needs for increased data processing capabilities of modern microprocessors, which, today, operate at clock frequencies up to 5 GHz [1] and have tens of cores in their more advanced versions [1]- [3]. Increased computational power of microprocessors has been achieved by reducing the transistors' gate widths to below 22 nm in recent technology nodes, leading to breakdown voltages of less than 1 V. However, the performance increase comes at the cost of increased power consumption, exceeding 150 W per device [4], and is accompanied by high supply currents reaching values close to 100 A considering a typical package voltage of 1.8 V [5]. In this regard, the concepts of independent Voltage Domains (VDs) for different cores or parts of the core and Dynamic Voltage and Frequency Scaling (DVFS) are effective countermeasures to reduce the power demands of microprocessors, since each core can be separately operated according to its workload.…”

Section: Introductionmentioning

confidence: 99%

Electrical and Thermal Characterization of an Inductor-Based ANPC-Type Buck Converter in 14 nm CMOS Technology for Microprocessor Applications

Bezerra

Krismer

Kolar

et al. 2020

IEEE Open J. Power Electron.

View full text Add to dashboard Cite

Integrated Voltage Regulators (IVRs) are attractive substitutes for conventional voltage regulators located on the motherboards, due to outstanding dynamic performances and superior power densities. IVRs operate with switching frequencies in the range of 100 MHz and are assembled in highly compact packages close to the microprocessor load. This paper presents a comprehensive characterization of a PCB-and inductorbased four-phase ANPC-type IVR that uses a Power Management IC (PMIC) implemented in a 14 nm CMOS technology node. The characterization is based on the results of electrical measurements, thermal inspections of the chip surface, and simulations, which enables the separation of the total losses into on-chip and off-chip loss components and the allocation of important loss components inside the chip. The investigated IVR achieves a maximum efficiency of 84.1 % at an output power of Pout = 640 mW and a switching frequency of fs = 50 MHz. The thermal measurements reveal that the maximum efficiency of the PMIC itself is between 88 % and 90 % at fs = 50 MHz and Pout ∈ [500 mW, 600 mW]; at Pout = 890 mW, a chip current density of 24.7 A/mm 2 is achieved. The findings in particular point out that the losses in the chip-internal interconnections, i.e., the conductors of the Power Distribution Network (PDN) and the twelve stacked metal layers below the PDN, have a substantial contribution to the total losses. Furthermore, the combination of Cadence post-layout simulations with impedance networks obtained from an appropriate software tool, e.g., FastHenry, is found to establish a suitable toolbox for estimating losses in IVRs.

show abstract

Power management in the Intel Xeon E5 v3

Cited by 14 publications

References 2 publications

FlexWatts: A Power- and Workload-Aware Hybrid Power Delivery Network for Energy-Efficient Microprocessors

FlexWatts: A Power- and Workload-Aware Hybrid Power Delivery Network for Energy-Efficient Microprocessors

A Comprehensive Evaluation of Power Delivery Schemes for Modern Microprocessors

Electrical and Thermal Characterization of an Inductor-Based ANPC-Type Buck Converter in 14 nm CMOS Technology for Microprocessor Applications

Contact Info

Product

Resources

About