Power measurement techniques on standard compute nodes: A quantitative comparison

Hackenberg, Daniel; Ilsche, Thomas; Schöne, Robert; Molka, Daniel; Schmidt, Michael; Nagel, Wolfgang E.

doi:10.1109/ispass.2013.6557170

Cited by 116 publications

(75 citation statements)

References 18 publications

(19 reference statements)

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“…This simple approach has been validated with hardware power meters by third parties studies for recent NVIDIA GPUs and Intel CPUs [15], showing that it produces accurate results [16,31]. In this approach we cannot monitor the power drain of the motherboard and other ancillary hardware; recent studies have shown however that the power drain of those components is approximately constant in time and weakly correlated with code execution [15,32]. In-band measurements may also introduce overheads, which in turn may affect our results.…”

Section: Methodsmentioning

confidence: 99%

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Evaluation of DVFS techniques on modern HPC processors and accelerators for energy‐aware applications

Calore

Gabbana

Schifano

et al. 2017

Concurrency and Computation

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SUMMARYEnergy efficiency is becoming increasingly important for computing systems, in particular for large scale HPC facilities. In this work we evaluate, from an user perspective, the use of Dynamic Voltage and Frequency Scaling (DVFS) techniques, assisted by the power and energy monitoring capabilities of modern processors in order to tune applications for energy efficiency. We run selected kernels and a full HPC application on two high-end processors widely used in the HPC context, namely an NVIDIA K80 GPU and an Intel Haswell CPU. We evaluate the available trade-offs between energy-to-solution and time-to-solution, attempting a function-by-function frequency tuning. We finally estimate the benefits obtainable running the full code on a HPC multi-GPU node, with respect to default clock frequency governors. We instrument our code to accurately monitor power consumption and execution time without the need of any additional hardware, and we enable it to change CPUs and GPUs clock frequencies while running. We analyze our results on the different architectures using a simple energy-performance model, and derive a number of energy saving strategies which can be easily adopted on recent high-end HPC systems for generic applications.

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Section: Methodsmentioning

confidence: 99%

“…732MHz) ≈ 7% of the total consumed energy of the computing node can be saved, with respect to the default behavior, without impacting performances. 15 …”

Section: Full Code On Multi-gpusmentioning

confidence: 99%

Evaluation of DVFS techniques on modern HPC processors and accelerators for energy‐aware applications

Calore

Gabbana

Schifano

et al. 2017

Concurrency and Computation

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“…One factor which hides the problems with Et n metrics is the small range of power consumption exhibited by modern hardware running HPC workloads as a result of high base power consumption and marginal differences under load [10]. Fig.…”

Section: Justification Of Et Nmentioning

confidence: 99%

Metrics for Energy-Aware Software Optimisation

Roberts

Wright

Fahmy

et al. 2017

Lecture Notes in Computer Science

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A note on versions:The version presented here may differ from the published version or, version of record, if you wish to cite this item you are advised to consult the publisher's version. Please see the 'permanent WRAP url' above for details on accessing the published version and note that access may require a subscription.For more information, please contact the WRAP Team at: wrap@warwick.ac.uk Metrics for Energy-Aware Software OptimisationStephen I. Roberts, Steven A. Wright, Suhaib A. Fahmy, and Stephen A. Jarvis University of Warwick, U.K. S.I.Roberts@warwick.ac.uk Abstract. Energy consumption is rapidly becoming a limiting factor in scientific computing. As a result, hardware manufacturers increasingly prioritise energy efficiency in their processor designs. Performance engineers are also beginning to explore software optimisation and hardware/software co-design as a means to reduce energy consumption. Energy efficiency metrics developed by the hardware community are often re-purposed to guide these software optimisation efforts. In this paper we argue that established metrics, and in particular those in the Energy Delay Product (Et n ) family, are unsuitable for energy-aware software optimisation. A good metric should provide meaningful values for a single experiment, allow fair comparison between experiments, and drive optimisation in a sensible direction. We show that Et n metrics are unable to fulfil these basic requirements and present suitable alternatives for guiding energy-aware software optimisation. We finish with a practical demonstration of the utility of our proposed metrics.

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“…The PowerMon2 [14] project describes small boards that can be used to instrument a large x86 cluster. Hackenberg et al [15] describe various power measurement techniques (including Intel running average power limit (RAPL) power estimates), but again, primarily looking at x86 devices.…”

Section: Cluster Power Measurementmentioning

confidence: 99%

A Raspberry Pi Cluster Instrumented for Fine-Grained Power Measurement

2016

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Abstract:Power consumption has become an increasingly important metric when building large supercomputing clusters. One way to reduce power usage in large clusters is to use low-power embedded processors rather than the more typical high-end server CPUs (central processing units). We investigate various power-related metrics for seventeen different embedded ARM development boards in order to judge the appropriateness of using them in a computing cluster. We then build a custom cluster out of Raspberry Pi boards, which is specially designed for per-node detailed power measurement. In addition to serving as an embedded cluster testbed, our cluster's power measurement, visualization and thermal features make it an excellent low-cost platform for education and experimentation.

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Power measurement techniques on standard compute nodes: A quantitative comparison

Cited by 116 publications

References 18 publications

Evaluation of DVFS techniques on modern HPC processors and accelerators for energy‐aware applications

Evaluation of DVFS techniques on modern HPC processors and accelerators for energy‐aware applications

Metrics for Energy-Aware Software Optimisation

A Raspberry Pi Cluster Instrumented for Fine-Grained Power Measurement

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