Power Modeling and Efficient FPGA Implementation of FHT for Signal Processing

Amira, Abbes; Chandrasekaran, S.

doi:10.1109/tvlsi.2007.893606

Cited by 33 publications

(15 citation statements)

References 19 publications

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“…The architecture was coded using VHDL which simulated by Xilinx ISE tool for functional validation and synthesized for implemented in different FPGA devices. Abbes Amira et al [8] had proposed a parameterizable and scalable architecture for fast Hadamard transform (FHT) with time and area complexities of O(2(W+1)) and O(2N2) respectively. Porto et al [9] presented a design space exploration on the forward 4x4 Hadamard Transform in H.264/AVC video coding standard.…”

Section: Literature Surveymentioning

confidence: 99%

FPGA Implementation of 4-Point and 8-Point Fast Hadamard Transform

Agrawal¹,

Bairathi²,

Joshi³

2015

IJCA

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Transformation is one of the fundamental blocks of many signal processing applications. The Hadamard transform is useful in variety of application including data encryption methods and latest data compression algorithms such as JPEG extended range (JPEG XR), High Efficiency Video Coding (HEVC) etc. Hadamard transform is multiplier less technique and requires additions and subtractions only. In this paper, we have proposed an efficient method of 4 and 8 points Hadamard transformation using a parallel processing to achieve higher speed. The 8-point DHT has been realized with 4 points DHT implementation. The modules are synthesized using Xilinx ISE 14.2 software with the usage of inbuilt memory core generator for storing co-efficient values. The performance has been verified with area and timing analysis. The proposed implementation shows excellent results and also compared to previous works.

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Section: Literature Surveymentioning

confidence: 99%

FPGA Implementation of 4-Point and 8-Point Fast Hadamard Transform

Agrawal¹,

Bairathi²,

Joshi³

2015

IJCA

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“…FPGA is also a programmability device, like programmable ROMs, and its programming techniques include antifuse-based device (Programmed Once) and static-memory-based device (Reprogrammed an Unlimited Number of Times). A typical FPGA consists of configurable logic blocks (CLB), input/output blocks (IOB), and programmable interconnects [4][5][6][7][8][9]. Each CLB can design the logical functions and latching data with combinational logic and sequential logic (AND, OR, Flipflops, and Registers).…”

Section: Fpga Development Environmentmentioning

confidence: 99%

“…It has been applied for digital filters design [4,5], signal analysis and classification [6,7], fault detection [8], and Fuzzy logic controller [9]. For signal analysis, transform methods have been used to extract features in the transform domain, such as fast Fourier transform (FFT) and wavelet transform (WT).…”

Section: Introductionmentioning

confidence: 99%

FPGA implementation of fractal patterns classifier for multiple cardiac arrhythmias detection

Lin¹,

Lin²

2012

JBiSE

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This paper proposes the fractal patterns classifier for multiple cardiac arrhythmias on field-programmable gate array (FPGA) device. Fractal dimension transformation (FDT) is employed to adjoin the fractal features of QRS-complex, including the supraventricular ectopic beat, bundle branch ectopic beat, and ventricular ectopic beat. FDT with fractal dimension (FD) is addressed for constructing various symptomatic patterns, which can produce family functions and enhance features, making clear differences between normal and unhealthy subjects. The probabilistic neural network (PNN) is proposed for recognizing multiple cardiac arrhythmias. Numerical experiments verify the efficiency and higher accuracy with the software simulation in order to formulate the mathematical model logical circuits. FDT results in data self-similarity for the same arrhythmia category, the number of dataset requirement and PNN architecture can be reduced. Its simplified model can be easily embedded in the FPGA chip. The prototype classifier is tested using the MIT-BIH arrhythmia database, and the tests reveal its practicality for monitoring ECG signals.

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“…These estimates are made even better in [13] by considering short-circuit power and leakage power. Comprehensive models for large parameterized IP generator based implementations have been presented in [14,15]. While [14] presents function-level area and power models for fast Hadamard transform (FHT).…”

Section: Introductionmentioning

confidence: 99%

“…Comprehensive models for large parameterized IP generator based implementations have been presented in [14,15]. While [14] presents function-level area and power models for fast Hadamard transform (FHT). Milder et al [15] presents area models for fully customizable discrete Fourier transform (DFT).…”

Section: Introductionmentioning

confidence: 99%

Accurate Area, Time and Power Models for FPGA-Based Implementations

Deng

Sobti

Zhang

et al. 2009

J Sign Process Syst

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This paper presents accurate area, time, power estimation models for implementations using FPGAs from the Xilinx Virtex-2Pro family (Deng et al. 2008). These models are designed to facilitate efficient design space exploration in an automated algorithmarchitecture codesign framework. Detailed models for estimating the number of slices, block RAMs and 18 × 18-bit multipliers for fixed point and floating point IP cores have been developed. These models are also utilized to develop power models that consider the effect of logic power, signal power, clock power and I/O power. Timing models have been developed to predict the latency of the fixed point and floating point IP cores. In all cases, the model coefficients have been derived by using curve fitting or regression analysis. The modeling error is quite small for single IP cores; the error for the area estimate, for instance, is on the This paper is an extension of the ICASSP'08 paper "Accurate Models for Estimating Area and Power of FPGA Implementations". average 0.95%. The error for fairly large examples such as floating point implementation of 8-point FFTs is also quite small; it is 1.87% for estimation of number of slices and 3.48% for estimation of power consumption. The proposed models have also been integrated into a hardware-software partitioning tool to facilitate design space exploration under area and time constraints.

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Power Modeling and Efficient FPGA Implementation of FHT for Signal Processing

Cited by 33 publications

References 19 publications

FPGA Implementation of 4-Point and 8-Point Fast Hadamard Transform

FPGA Implementation of 4-Point and 8-Point Fast Hadamard Transform

FPGA implementation of fractal patterns classifier for multiple cardiac arrhythmias detection

Accurate Area, Time and Power Models for FPGA-Based Implementations

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