Power optimisation using intelligent Clock gating dedicated for block RAM cascading technique in FPGA design.

Abstract

The current trend is the combination of chip size reduction and an increase in the number of circuits on chips has provided significant growth in battery consumption and critical energy efficiency leading to growth in the emerging Low Power Electronics sector. Our paper is committed to optimizing the power by eliminating cascading in block RAM. It dominates the amount of power dissipated in SOCs (System on Chips). High-level integration (HLS) allows hardware designers to think logically and not worry about low-level, cyclical details. It arranges the capability to quickly access the slot of design and the tradeoff between resource utilization and operation. Field Programmable Gate Arrays (FP- GAs) show significant progress in measuring speed and capacity to create a platform for the use of digital circuits. In the design of the FPGA, integration tools are used that perform various mitigation and improvement strategies. Integration tools utilize the RTL representation of a project with time constraints and generate a network list of the same level. Today, the advanced Xilinx Vivado Design Suite is used for FPGA design as a blending tool. In some cases, the Xilinx Vivado is unable to meet the required designer delays and power constraints. Therefore the primary goal of this paper is to optimize the power in design constraints in the Xilinx Vivado software.

Low Power Low-Density Parity Check Encoder Using Dynamic Voltage and Frequency Scaling Approach

“…With a wide variety of strategies for reducing energy usage specialized for microprocessors and Complementary Metal-Oxide-Semiconductor (CMOS) circuits such as energy gating (shutdown) [10], clock gating method (sleep mood) [11], and Dynamic Voltage and Frequency Scaling (DVFS) [12], Attempting to integrate these technologies with networking is an attractive manner. This paper aims to implement DVFS on the LDPC circuit so that the power consumption of the LDPC circuit is minimized regardless of the frequency used and the communication standard.…”