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The article presents the comprehensive approach of designing MDM in Inter‐Satellite OWC system using CSRZ‐DQPSK, DRZ‐DQPSK, and MDRZ‐DQPSK modulation system. The 64 Laguerre Gaussian modes are integrated to enhance the system's capability. The proposed system is designed for 64 channels having distances varied from 900 to 4500 km at various data rates. The mode division multiplexing concept is implemented over WDM because it uses single laser source and enhance the capacity of optical networks. Performance of proposed system is examined by comparing the eye diagrams and Q‐factor. It is observed from the outcomes that MDRZ‐DQPSK modulation presents superior Quality factor of 19.42 then DRZ‐DQPSK and CSRZ‐DQPSK Modulation with the favorable distance upto 4500 km at 10 Gbps bit rate. MDRZ‐DQPSK modulation technique performs well till 40 Gbps whereas CSRZ‐DQPSK Modulation exhibits least Q‐factor due to high consumption of bandwidth but it saves cost and preferable for long reach transmission.

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The current trend is the combination of chip size reduction and an increase in the number of circuits on chips has provided significant growth in battery consumption and critical energy efficiency leading to growth in the emerging Low Power Electronics sector. Our paper is committed to optimizing the power by eliminating cascading in block RAM. It dominates the amount of power dissipated in SOCs (System on Chips). High-level integration (HLS) allows hardware designers to think logically and not worry about low-level, cyclical details. It arranges the capability to quickly access the slot of design and the tradeoff between resource utilization and operation. Field Programmable Gate Arrays (FP- GAs) show significant progress in measuring speed and capacity to create a platform for the use of digital circuits. In the design of the FPGA, integration tools are used that perform various mitigation and improvement strategies. Integration tools utilize the RTL representation of a project with time constraints and generate a network list of the same level. Today, the advanced Xilinx Vivado Design Suite is used for FPGA design as a blending tool. In some cases, the Xilinx Vivado is unable to meet the required designer delays and power constraints. Therefore the primary goal of this paper is to optimize the power in design constraints in the Xilinx Vivado software.