Power Optimization of VLSI Scan under Test using X-Filling Technique

Priya, A. Swetha; Kamatchi, S.

doi:10.1109/eti4.051663.2021.9619269

Cited by 7 publications

(2 citation statements)

References 22 publications

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“…The basic x-filling algorithms replace the unspecified bits with either 0 or 1 or adjacent bits, which minimizes SA. Techniques presented in [45]- [47] use these algorithms to create pattern sets with reduced shift power. It calculates power consumption for each pattern using them and chooses the patterns which produce the least switching while maintaining fault coverage.…”

Section: Ordering Chains Using Both Logic Connectivity and Pattern Co...mentioning

confidence: 99%

Developments in scan shift power reduction: a survey

Sontakke,

Dickhoff

2023

Bulletin EEI

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While power reduction during testing is necessary for today's low-power devices, it also lowers test costs. Scan-based methods are the most widely used approach for testing integrated circuits (IC). Test vectors are shifted into and out of scan chains bit by bit during shift operation. The time required for shift operation dominates the test time. With the geometries shrinking (7 nm→5 nm→3 nm→1.8 nm), ICs are required to be tested for newer defects, increasing test time. The most effective way to reduce test time for scan operation is to increase the frequency of the shift operation. Reduction in shift power enables scan operation to be performed with increased frequency, reducing test time, and test cost. This paper presents a survey of techniques proposed recently for shift power reduction. Various techniques, including special flip-flop usage, segmentation, reordering, and low-pass filter, are being reviewed. The techniques are organized based on main attributes to underscore their similarities and differences. Pros and cons in terms of complexities involved in their implementation are discussed. We believe this paper will provide a point of reference for further studies in scan shift power reduction and will be helpful to both industry and academia.

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Section: Ordering Chains Using Both Logic Connectivity and Pattern Co...mentioning

confidence: 99%

Developments in scan shift power reduction: a survey

Sontakke,

Dickhoff

2023

Bulletin EEI

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“…The technique has shown a reduction in average shift and average capture power. Techniques presented in [35], [36] also use different filling methods and choose the pattern with lesser switching activity.…”

Section: Evaluating and Choosing X-fillmentioning

confidence: 99%

A survey of scan-capture power reduction techniques

Sontakke,

Dickhoff

2023

IJECE

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With the advent of sub-nanometer geometries, integrated circuits (ICs) are required to be checked for newer defects. While scan-based architectures help detect these defects using newer fault models, test data inflation happens, increasing test time and test cost. An automatic test pattern generator (ATPG) exercise’s multiple fault sites simultaneously to reduce test data which causes elevated switching activity during the capture cycle. The switching activity results in an IR drop exceeding the devices under test (DUT) specification. An increase in IR-drop leads to failure of the patterns and may cause good DUTs to fail the test. The problem is severe during at-speed scan testing, which uses a functional rated clock with a high frequency for the capture operation. Researchers have proposed several techniques to reduce capture power. They used various methods, including the reduction of switching activity. This paper reviews the recently proposed techniques. The principle, algorithm, and architecture used in them are discussed, along with key advantages and limitations. In addition, it provides a classification of the techniques based on the method used and its application. The goal is to present a survey of the techniques and prepare a platform for future development in capture power reduction during scan testing.

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