Power optimization using dynamic power management

Monteiro, José

doi:10.1109/sbcci.1999.803105

Cited by 8 publications

(7 citation statements)

References 14 publications

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“…CG assumes using an additional clock logic (CL) block [3]. This logic is based on the precomputation of inputs being disabled [73,74].…”

Section: Saving Power By Clock-gating and Fsm Decompositionmentioning

confidence: 99%

“…These approaches are shown in Figure 10. Both methods of parallel (Figure 10a) and cascade (Figure 10b) decomposition have rather theoretical value [3]. But the general decomposition (Figure 10c) can be used for any FSM.…”

Section: Saving Power By Clock-gating and Fsm Decompositionmentioning

confidence: 99%

“…They should consume as little power as possible [2]. It means that power consumption has become a primary concern in the design of integrated circuits [3]. Two main issues are connected with this demand.…”

Section: Introductionmentioning

confidence: 99%

“…To control the values of V dd and f op , various methods of dynamic voltage and frequency scaling (DVFS) can be used [3]. Also, it can be done using low-power modes.…”

mentioning

confidence: 99%

“…In [3], this approach is combined with clock gating for both inputs and state registers. This combines approaches from [76,77] with some new approach.…”

mentioning

confidence: 99%

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Basic Approaches for Reducing Power Consumption in Finite State Machine Circuits—A Review

Barkalov,

Titarenko,

Bieganowski

et al. 2024

Applied Sciences

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Methods for reducing power consumption in circuits of finite state machines (FSMs) are discussed in this review. The review outlines the main approaches to solving this problem that have been developed over the last 40 years. The main sources of power dissipation in CMOS circuits are shown; the static and dynamic components of this phenomenon are analyzed. The power consumption saving can be achieved by using coarse-grained methods common to all digital systems. These methods are based on voltage or/and clock frequency scaling. The review shows the main structural diagrams generated by the use of these methods when optimizing the power characteristics of FSM circuits. Also, there are various known fine-grained methods taking into account the specifics of both FSMs and logic elements used. Three groups of the fine-grained methods targeting FPGA-based FSM circuits are analyzed. These groups include clock gating, state assignment, and replacing look-up table (LUT) elements by embedded memory blocks (EMBs). The clock gating involves a separate or joint use of such approaches as the (1) decomposition of FSM inputs and (2) disabling FSM inputs. The aim of the power-saving state assignment is to reduce the switching activity of a resulting FSM circuit. The replacement of LUTs by EMBs allows a reduction in the power consumption due to a decrease in the number of FSM circuit elements and their interconnections. We hope that the review will help experts to use known methods and develop new ones for reducing power consumption. We think that a good knowledge and understanding of existing methods of reducing power consumption is a prerequisite for the development of new, more effective methods to solve this very important problem. Although the methods considered are mainly aimed at FPGA-based FSMs, they can be modified, if necessary, and used for the power consumption optimization of FSM circuits implemented with other logic elements.

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“…CG assumes using an additional clock logic (CL) block [3]. This logic is based on the precomputation of inputs being disabled [73,74].…”

Section: Saving Power By Clock-gating and Fsm Decompositionmentioning

confidence: 99%

Section: Saving Power By Clock-gating and Fsm Decompositionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

“…To control the values of V dd and f op , various methods of dynamic voltage and frequency scaling (DVFS) can be used [3]. Also, it can be done using low-power modes.…”

mentioning

confidence: 99%

“…In [3], this approach is combined with clock gating for both inputs and state registers. This combines approaches from [76,77] with some new approach.…”

mentioning

confidence: 99%

See 3 more Smart Citations

Basic Approaches for Reducing Power Consumption in Finite State Machine Circuits—A Review

Barkalov,

Titarenko,

Bieganowski

et al. 2024

Applied Sciences

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Power minimisation techniques at the RT-level and below

Abdollahi

Pedram

2006

System-on-Chip: Next Generation Electronics

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A dichotomy exists in the design of modern microelectronic systems: they must be low power and high performance, simultaneously. This dichotomy largely arises from the use of these systems in battery-operated portable (wearable) platforms. Accordingly, the goal of low-power design for battery-powered electronics is to extend the battery service life while meeting performance requirements. Unless optimisations are applied at different levels, the capabilities of future portable systems will be severely limited by the weight of the batteries required for an acceptable duration of service. In fixed, power-rich platforms, the packaging cost and power density/reliability issues associated with high power and high performance systems also force designers to look for ways to reduce power consumption. Thus, reducing power dissipation is a design goal even for non-portable devices since excessive power dissipation results in increased packaging and cooling costs as well as potential reliability problems. Meanwhile, following Moore's Law, integrated circuit densities and operating speeds have continued to go up in unabated fashion. The result is that chips are becoming larger, faster and more complex and because of this, consuming increasing amounts of power.These increases in power pose new and difficult challenges for integrated circuit designers. While the initial response to increasing levels of power consumption was to reduce the supply voltage, it quickly became apparent that this approach was insufficient. Designers subsequently began to focus on advanced design tools and methodologies to address the myriad of power issues. Complicating designers' attempts to deal with these issues are the complexities -logical,

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Low power 32-bit UniRISC with Power Block Manager

Hsiao

Chu

et al. 2008

APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems

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Power optimization using dynamic power management

Cited by 8 publications

References 14 publications

Basic Approaches for Reducing Power Consumption in Finite State Machine Circuits—A Review

Basic Approaches for Reducing Power Consumption in Finite State Machine Circuits—A Review

Power minimisation techniques at the RT-level and below

Low power 32-bit UniRISC with Power Block Manager

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