Power optimizations for transport triggered SIMD processors

Abstract

Power consumption in modern processor design is a key aspect. Optimizing the processor for power leads to direct savings in battery energy consumption in case of mobile devices. At the same time, many mobile applications demand high computational performance. In case of large scale computing, low power compute devices help in thermal design and in reducing the electricity bill. This paper presents a case study of a customized low power vector processor design that was synthesized on a 28 nm process technology. The processor has a programmer exposed datapath based on the transport triggered architecture programming model. The paper's focus is on the RTL and microarchitecture level power optimizations applied to the design. Using semiautomated interconnection network and register file optimization algorithm, up to 27% of power savings were achieved. Using this as a baseline and applying register file datapath gating, register file banking and enabling clock gating of individual pipeline stages in pipelined function units, up to 26% of power and energy savings could be achieved with only a 3% area overhead. On top of this, for the measured radio applications, the exposed datapath architecture helped to achieve approximately 18% power improvement in comparison to a VLIW-like architecture by utilizing optimizations unique to transport triggered architectures.

Evaluation of Different Processor Architecture Organizations for On-Site Electronics in Harsh Environments

“…As a drawback, the TTA programming model requires large instruction widths of up to 112 bit, increasing the silicon area of the instruction memory and the power consumption. However, mechanisms like instruction register files, variable length encoding, and loop buffers [23,24,33] could be applied in future work to mitigate the effects on area and power consumption. Compared to the ARM Cortex-M0, the transporttriggered architecture configuration C12 has an 8.59 higher performance and 2.49 higher computational energy efficiency at a 1.69 larger total silicon area, showing the considerable range of design trade-offs for different architectures.…”

LordCore: Energy-Efficient OpenCL-Programmable Software-Defined Radio Coprocessor

“…Table II shows the estimated power and energy efficiency of the quadcore system. In general, 22.0% of the power is consumed by vector execution units, 8.3% by the vector register file, 2.1% by the scalar ALUs and scalar registers, 8.5% by the interconnect network, 26% by the global memory, 16.9% by The effect on the TTA-specific optimizations on the power consumption was analyzed in preliminary work in [50]. The TTA-specific optimizations provided on average 18% decrease in power consumption in these workloads.…”