Power reduction using high speed with saving mode clock gating technique

Hameed, Maan; Mogheer, Hussein Sh.; Mansour, Ali

doi:10.1088/1757-899x/1076/1/012055

Cited by 7 publications

(4 citation statements)

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“…Clock gating is achieved with Flip-flops, latches, AND/OR gate in the clock signal and a control signal to construct of gated clock signal, then be relevant to distinct components of the circuit. Exception to Power, there are two other parameters also optimized in an 8-bit ALU circuit i.e., Area and Delay are reduced with Clock delay [11], [12].…”

Section: Problem Formulationmentioning

confidence: 99%

VLSI Synthesis for Low-Power Clocking in Synchronous Designs

Hussein,

Hameed,

Khamees

2024

IJOIR

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In the field of information theory, the significance of low-power techniques cannot be overstated. Among these, clock gating stands out as a potent method to mitigate power dissipation in synchronous designs. The landscape has been further shaped by VLSI innovations, which, in their initial stages, necessitated substantial equipment, incurred high power consumption, and exhibited occasional unreliability. This paper explores the evolution from these challenges to a paradigm where advancements in VLSI technology have resulted in smaller, more affordable, reliable, and power-efficient systems. Focusing on the Arithmetic Logical Unit (ALU) design, our study presents a comparative analysis of power consumption across various existing clock gating techniques. Introducing an innovative signal clock gating method, we address contemporary challenges with an accessible mechanism, enhancing immunity. Our proposed Gated Clock Generation design, employing a tri-state connection and logic gate, demonstrates superior power savings, even when applied to the target module. This approach optimizes power efficiency in digital design while proving particularly effective in reducing dynamic power within logic circuits. Implementing an improved gate-based clock gating technique in ALU design, our results show a noteworthy reduction in clock delay (71% to 78%), a 23% improvement in area, and a substantial 66.67% enhancement in power efficiency. Notably, this clock gating scheme surpasses alternative methods in terms of area requirements. The experiments, exclusively conducted on ALU design, utilized 130 nm standard logic libraries for implementation. The design architecture was meticulously crafted using Verilog HDL, and simulations were executed with ModelSim-Altera 10.0c (Quartus II 11.1) Starter Version.

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Section: Problem Formulationmentioning

confidence: 99%

VLSI Synthesis for Low-Power Clocking in Synchronous Designs

Hussein,

Hameed,

Khamees

2024

IJOIR

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“…Adding a gated clock in ALU can reduce the dynamic power consumption of the chip. It reduces power consumption by closing sub-logic and sub-components [10]. The design of the ALU is shown in Figure 3, which is mainly to add an enable signal at each signal input.…”

Section: Clock-gatedmentioning

confidence: 99%

Optimization of ALU with gated clock and its internal modules in RVIM64 processor

Zhu,

Liu,

Zhang

et al. 2023

J. Phys.: Conf. Ser.

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Low power consumption and area are the main research directions of the RISC-V architecture processor, and the arithmetic logic operation unit (ALU) is the key part that affects the overall performance of the processor. In order to improve the performance of the RISC-V architecture processor, we adopted the strategy of reducing the overall power consumption and area of ALU, by using the method of adding a gated clock circuit and optimizing the structure of the comparison module and shift module in ALU. Under the conditions of 90 nm technology, the temperature and the voltage were set to 125 °C and 1 V respectively. The synthesis results of ALU are as follows: the area is 111061 um2, the power consumption is 20.58 MW, and the delay is 20.58 ps. Compared with other traditional ALU, the area is reduced by 46%, and power consumption is reduced by about 48%.

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“…The new Gated Clock signal produced is shown in Figure ( 4) using the tri-state buffer connection and the connected bubbled input NAND gate in order to achieve this goal. In such an operation, this method holds power even when the clock of the target device is on, the clock of the controlling device is off, and even when the clock of the target device is off also the clock of the controlling device is off [17]. The goal design will save additional power in these procedures by preventing unused clock signal switching operation [18].…”

Section: A New Technology Of Clock Gatingmentioning

confidence: 99%

A New Technology for Reducing Dynamic Power Consumption in 8-Bit ALU Design

Hameed¹,

Hameed²,

Hasan³

2022

IJOIR

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Clock gating is an effective way to decrease dissipated power in synchronous design. The most effective way to do this is by masking the clock that turns toward the unused part of design. In this paper, a comparative evaluation of power consumption in existing clock gating techniques in Arithmetic Logical Unit (ALU) design was achieved. an innovative signal clock gating method offers extra immunity in the direction of the present issue in an accessible mechanism. A Gated Clock Generation designs using a tri-state connection and logic gate, generated by the set of bubbled input with NAND gate, is used for the latest suggested clock gating. This design saves power even when the clock is at applying to the target module. Complete power analysis reveals that the proposed technique has an effect on the dynamic power that decreases total power consumption up to 24.90% relative to traditional power. All experiments are done in arithmetic logic unit design. 130 nm standard logic libraries have been used for implementation in order to achieve ALU frameworks. The ALU design architecture was developed using the Verilog HDL, and the simulations are performed utilizing ModelSim-Altera 10.0c (Quartus II 11.1) Starter Version.

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Power reduction using high speed with saving mode clock gating technique

Cited by 7 publications

References 0 publications

VLSI Synthesis for Low-Power Clocking in Synchronous Designs

VLSI Synthesis for Low-Power Clocking in Synchronous Designs

Optimization of ALU with gated clock and its internal modules in RVIM64 processor

A New Technology for Reducing Dynamic Power Consumption in 8-Bit ALU Design

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