The demand for low power consumption is motivated by several factors such as the evolution of portable design, reliability effects, and flexibility. The purpose of clock gating is inactive or suppresses change to fragments of the clock route as flip-flop, clock system and rationality under a specific condition processed by clock gating chips. Moreover, the clock is disabled when it is not necessary in clock gating to decrease power dissipation. Clock technique successfully turns off the clock any place it pointlessly expends power. By following the expressed methodology, the force utilization turns out to be less up to half without influencing the performance of the structure. The extraordinary source of power utilization is the clock. Clock signal is not used to achieve any digital calculation. It is for the most part utilized for synchronization of successive circuits. In this way, clock signal does not carry any data. In this research paper, a new sub module for high speed and saving mode is proposed. It saves more power by switch on only the target module and switch other module off. By using this technique, it may reduce power dissipation up to half. In order to execute encoder and decoder structure, the models of compression and decompression process is created by applying Verilog HDL language Quartus II 11.1 Web Edition with 32-Bit. In addition, operational simulation is executed by using ModelSim-Altera 10.0c (Quartus II 11.1 Starter Edition).

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Clock gating is an effective way to decrease dissipated power in synchronous design. The most effective way to do this is by masking the clock that turns toward the unused part of design. In this paper, a comparative evaluation of power consumption in existing clock gating techniques in Arithmetic Logical Unit (ALU) design was achieved. an innovative signal clock gating method offers extra immunity in the direction of the present issue in an accessible mechanism. A Gated Clock Generation designs using a tri-state connection and logic gate, generated by the set of bubbled input with NAND gate, is used for the latest suggested clock gating. This design saves power even when the clock is at applying to the target module. Complete power analysis reveals that the proposed technique has an effect on the dynamic power that decreases total power consumption up to 24.90% relative to traditional power.  All experiments are done in arithmetic logic unit design. 130 nm standard logic libraries have been used for implementation in order to achieve ALU frameworks. The ALU design architecture was developed using the Verilog HDL, and the simulations are performed utilizing ModelSim-Altera 10.0c (Quartus II 11.1) Starter Version.