Power Side Channel Resistance of RNS Secure Logic

Selvam, Ravikumar; Tyagi, Akhilesh K.

doi:10.1109/vlsid.2018.52

Cited by 7 publications

(6 citation statements)

References 12 publications

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“…Improving the efficiency of the comparison operation in RNS is something that can be used in the development of new approaches to the implementation of other problematic operations in RNS, such as subtraction-based division and the detection of dynamic range overflow. Dynamic range overflow detectors in RNS are widely applied in the design of fault-tolerant systems and secure communication channels [17].The state-of-the-art in the described problem is as follows. The most common approaches to performing non-modular RNS operations are based on mixed radix conversion (MRC) and the Chinese remainder theorem (CRT) [1,18].…”

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Construction of Residue Number System Using Hardware Efficient Diagonal Function

et al. 2019

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The residue number system (RNS) is a non-positional number system that allows one to perform addition and multiplication operations fast and in parallel. However, because the RNS is a non-positional number system, magnitude comparison of numbers in RNS form is impossible, so a division operation and an operation of reverse conversion into a positional form containing magnitude comparison operations are impossible too. Therefore, RNS has disadvantages in that some operations in RNS, such as reverse conversion into positional form, magnitude comparison, and division of numbers are problematic. One of the approaches to solve this problem is using the diagonal function (DF). In this paper, we propose a method of RNS construction with a convenient form of DF, which leads to the calculations modulo 2 n , 2 n − 1 or 2 n + 1 and allows us to design efficient hardware implementations. We constructed a hardware simulation of magnitude comparison and reverse conversion into a positional form using RNS with different moduli sets constructed by our proposed method, and used different approaches to perform magnitude comparison and reverse conversion: DF, Chinese remainder theorem (CRT) and CRT with fractional values (CRTf). Hardware modeling was performed on Xilinx Artix 7 xc7a200tfbg484-2 in Vivado 2016.3 and the strategy of synthesis was highly area optimized. The hardware simulation of magnitude comparison shows that, for three moduli, the proposed method allows us to reduce hardware resources by 5.98-49.72% in comparison with known methods. For the four moduli, the proposed method reduces delay by 4.92-21.95% and hardware costs by twice as much by comparison to known methods. A comparison of simulation results from the proposed moduli sets and balanced moduli sets shows that the use of these proposed moduli sets allows up to twice the reduction in circuit delay, although, in several cases, it requires more hardware resources than balanced moduli sets. such as field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC). All these attractive features increase interest to RNS in the areas where large amounts of computation are needed. The applications of RNS are digital signal processing [2][3][4], cryptography [5][6][7], digital image processing [8], cloud computing [9], Internet of Things [10] and others. In [11], the authors propose a technique to estimate real-valued numbers by means of the Chinese remainder theorem (CRT), employing for this goal a Kroenecker based M-Estimation, to improve robustness. A new method based on the Chinese remainder theorem (CRT) is proposed for absolute position computation in [12]. This has advantages in terms of hardware and flexibility because it does not use memory. The authors of [13] offer to use RNS to improve the performance of the convolutional neural network developed for pattern recognition tasks. Reference [14] describes the method of construction for finite impulse response filers using RNS.However, the limitations of RNS include some operations such a...

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Construction of Residue Number System Using Hardware Efficient Diagonal Function

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“…Dual rail logic provides strong side-channel privacy, but no cryptographic privacy. The RNS logic [21,22] combines both side-channel privacy and cryptographic privacy. There is an average reduction of 25% in the adversary's machine learning success rate in leaking a block encryption secret with the RNS logic.…”

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Residue Number System (RNS) and Power Distribution Network Topology-Based Mitigation of Power Side-Channel Attacks

Selvam,

Tyagi

2023

Cryptography

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Over the past decade, significant research has been performed on power side-channel mitigation techniques. Logic families based on secret sharing schemes, such as t-private logic, that serve to secure cryptographic implementations against power side-channel attacks represent one such countermeasure. These mitigation techniques are applicable at various design abstraction levels—algorithm, architecture, logic, physical, and gate levels. One research question is when can the two mitigation techniques from different design abstraction levels be employed together gainfully? We explore this notion of the orthogonality of two mitigation techniques with respect to the RNS secure logic, a logic level power side-channel mitigation technique, and power distribution network (PDN), with the decoupling capacitance, a mitigation technique at physical level. Machine learning (ML) algorithms are employed to measure the effectiveness of power side-channel attacks in terms of the success rate of the adversary. The RNS protected LED block cipher round function is implemented as the test circuit in both tree-style and grid-style PDN using the FreePDK 45 nm technology library. The results show that the success rate of an unsecured base design 68.96% for naive Bayes, 67.44% with linear discriminant analysis, 67.51% for quadratic discriminant analysis, and 66.58% for support vector machine. It is reduced to a success rate of 19.68% for naive Bayes, 19.62% with linear discriminant analysis, 19.10% for quadratic discriminant analysis, and 10.54% in support vector machine. Grid-type PDN shows a slightly better reduction in success rate compared to the tree-style PDN.

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“…We speculate that cryptographic privacy, even if not directly addressing power uniformity, thwarts power side-channel attacks. An interesting trade-off between power side-channel privacy and cryptographic privacy to minimize the success rate of a power side-channel adversary exists, which we explored and discussed in [ 26 ] (the cited paper is the conference version of current work with preliminary results which was published in IEEE 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, VLSID 2018).…”

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An Evaluation of Power Side-Channel Resistance for RNS Secure Logic

Selvam

Tyagi

2022

Sensors

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In this paper, residue number system (RNS) based logic is proposed as a protection against power side-channel attacks. Every input to RNS logic is encrypted as a share of the original input in the residue domain through modulus values. Most existing countermeasures enhance side-channel privacy by making the power trace statistically indistinguishable. The proposed RNS logic provides cryptographic privacy that also offers side-channel resistance. It also offers side-channel privacy by mapping different input bit values into similar bit encodings for the shares. This property is also captured as a symmetry measure in the paper. This side-channel resistance of the RNS secure logic is evaluated analytically and empirically. An analytical metric is developed to capture the conditional probability of the input bit state given the residue state visible to the adversary, but derived from hidden cryptographic secrets. The transition probability, normalized variance, and Kullback–Leibler (KL) divergence serve as side-channel metrics. The results show that our RNS secure logic provides better resistance against high-order side-channel attacks both in terms of power distribution uniformity and success rates of machine learning (ML)-based power side-channel attacks. We performed SPICE simulations on Montgomery modular multiplication and Arithmetic-style modular multiplication using the FreePDK 45 nm Technology library. The simulation results show that the side-channel security metrics using KL divergence are 0.0204 for Montgomery and 0.0020 for the Arithmetic-style implementation. This means that Arithmetic-style implementation has better side-channel resistance than the Montgomery implementation. In addition, we evaluated the security of the AES encryption with RNS secure logic on a Spartan-6 FPGA Board. Experimental results show that the protected AES circuit offers 79% higher resistance compared to the unprotected AES circuit.

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Power Side Channel Resistance of RNS Secure Logic

Cited by 7 publications

References 12 publications

Construction of Residue Number System Using Hardware Efficient Diagonal Function

Construction of Residue Number System Using Hardware Efficient Diagonal Function

Residue Number System (RNS) and Power Distribution Network Topology-Based Mitigation of Power Side-Channel Attacks

An Evaluation of Power Side-Channel Resistance for RNS Secure Logic

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