Power Virus Generation Using Behavioral Models of Circuits

Najeeb, K.; Vardhan, V. Vishnu; Konda, Ramakrishna; Kumar, Sumit; Hari, Siva Kumar Sastry; Kamakoti, V.; Vedula, V.M.

doi:10.1109/vts.2007.49

Cited by 21 publications

(4 citation statements)

References 9 publications

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“…For instance, if we know that a particular part of the system is vulnerable to subtle failures, an SLT workload that stresses this part of the system will be useful. This is related to the "power-virus" generation considered (for much smaller circuits) in the past [27].…”

Section: Slt Program Generationmentioning

confidence: 99%

Exploring the Mysteries of System-Level Test

Polian,

Anders,

Becker

et al. 2021

Preprint

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System-level test, or SLT, is an increasingly important process step in today's integrated circuit testing flows. Broadly speaking, SLT aims at executing functional workloads in operational modes. In this paper, we consolidate available knowledge about what SLT is precisely and why it is used despite its considerable costs and complexities. We discuss the types or failures covered by SLT, and outline approaches to quality assessment, test generation and root-cause diagnosis in the context of SLT. Observing that the theoretical understanding for all these questions has not yet reached the level of maturity of the more conventional structural and functional test methods, we outline new and promising directions for methodical developments leveraging on recent findings from software engineering.

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Section: Slt Program Generationmentioning

confidence: 99%

Exploring the Mysteries of System-Level Test

Polian,

Anders,

Becker

et al. 2021

Preprint

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“…The technique is also functionally valid at the processor level. Najeeb et al [34] propose a technique that converts a circuit behavioral model to an integer constraint model and employs an integer constraint solver to generate a power virus that can be used to estimate the peak power of the processor. To the best of our knowledge, no prior work exists on determining application-specific peak power for a processor based on symbolic simulation.…”

Section: Related Workmentioning

confidence: 99%

Determining Application-specific Peak Power and Energy Requirements for Ultra-low Power Processors

Cherupalli

Duwe

et al. 2017

SIGPLAN Not.

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Many emerging applications such as IoT, wearables, implantables, and sensor networks are power-and energyconstrained. These applications rely on ultra-low-power processors that have rapidly become the most abundant type of processor manufactured today. In the ultra-low-power embedded systems used by these applications, peak power and energy requirements are the primary factors that determine critical system characteristics, such as size, weight, cost, and lifetime. While the power and energy requirements of these systems tend to be application-specific, conventional techniques for rating peak power and energy cannot accurately bound the power and energy requirements of an application running on a processor, leading to over-provisioning that increases system size and weight. In this paper, we present an automated technique that performs hardware-software coanalysis of the application and ultra-low-power processor in an embedded system to determine application-specific peak power and energy requirements. Our technique provides more accurate, tighter bounds than conventional techniques for determining peak power and energy requirements, reporting 15% lower peak power and 17% lower peak energy, on average, than a conventional approach based on profiling and guardbanding. Compared to an aggressive stressmarkbased approach, our technique reports power and energy bounds that are 26% and 26% lower, respectively, on average. Also, unlike conventional approaches, our technique reports guaranteed bounds on peak power and energy independent of an application's input set. Tighter bounds on peak power and energy can be exploited to reduce system size, weight, and cost.

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“…Thus, the generated sequence will result in an unrealistic estimation [12]. The techniques presented in [13] and [14] attempt to find the assembly instructions for determining the peak power, but neither do they perform a full-chip power distribution network simulation, nor do they consider the resistance of conductors and the location of power pads. The authors of [15] and [16] propose methods to generate the input patterns to maximize the high-frequency supply noise (noise frequency S clock frequency).…”

Section: Introductionmentioning

confidence: 99%

Estimation of maximum application-level power supply noise

Sambamurthy

Abraham

2010

23rd IEEE International SOC Conference

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This paper presents a systematic technique that relates the instructions at the application-level to the cycle average supply noise. Cost metrics affecting supply noise are maximized and the corresponding activity event is mapped to instructions. We performed experiments on an open-source processor and were able to obtain a higher voltage drop (> 20%) when compared to that of random simulation in a significantly less amount of time (96% reduction).

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Power Virus Generation Using Behavioral Models of Circuits

Cited by 21 publications

References 9 publications

Exploring the Mysteries of System-Level Test

Exploring the Mysteries of System-Level Test

Determining Application-specific Peak Power and Energy Requirements for Ultra-low Power Processors

Estimation of maximum application-level power supply noise

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