Power vs. delay in gate sizing: conflicting objectives?

Sapatnekar, Sachin S.; Chuang, Weitong

doi:10.1109/iccad.1995.480157

Cited by 24 publications

(12 citation statements)

References 9 publications

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“…In this representation the delay of the gate (i) is evaluated from tllL,LH (i)= A'tIN + tllLS,LHS (i)(l-Cor») (1) where 'tIN is the input control ramp duration, tHL,LHS the fall or rise step response of the switching gate, Cor a correcting term associated to the carrier speed saturation induced non linear variation of submicron process and A, a process dependent constant term [16].…”

Section: Modelingmentioning

confidence: 99%

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Feasible delay bound definition

Azémard

Aline

Maurine

et al. 2002

IFIP Advances in Information and Communication Technology

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Abstract:Minimizing the number of iterations when satisfying performance constraints in Ie design is of fundamental importance to limit the design iterations. We present a method to determine the feasibility of delay constraint imposed on circuit path. From a layout oriented study of the path delay distribution, we show how to obtain the upper and lower bounds of the delay of combinatorial paths. Then we characterise these bounds and present a method to determine, , the average weighted loading factor allowing to satisfy the delay constraint.Example of application is given on different ISeAS circuits.

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Section: Modelingmentioning

confidence: 99%

“…Great interest [1][2][3][4] has been given to the research of optimal solutions to the problem of transistor sizing under delay constraint. But very few information is available on the direct determination of bounds on delay [5] allowing to evaluate the feasibility of constraints and/or the efficiency of an implementation.…”

Section: Introductionmentioning

confidence: 99%

Feasible delay bound definition

Azémard

Aline

Maurine

et al. 2002

IFIP Advances in Information and Communication Technology

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show abstract

“…A great effort has been developed to find optimal solutions to the problem of transistor sizing under delay constraint using global or local optimization heuristics [1][2][3][4] . But few information is available on direct determination of bounds on delay 5,6 allowing to evaluate the feasibility of constraints or the efficiency of an implementation.…”

Section: Introductionmentioning

confidence: 99%

Delay-bound determination for path constraint satisfaction

2000

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This paper addresses the problem of path constraint satisfaction from delay bound determination. Based on a path delay profiling tool a method is developed to determine the feasibility of delay constraint imposed on circuit path. From the evolution of the path delay profile with transistor sizing conditions, upper and lower bounds of delay are defined and characterized in terms of loading factors. Using these bounds as a reference, a method is developed to define average loading factor and equivalently transistor size allowing to satisfy timing constraint on critical path. Examples of application are given on different ISCAS circuits.

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“…Conventional approaches for power reduction optimize the amount of capacitive load [4,6] or the amount of capacitive load and short-circuit current [5,7] based on the transition activity information obtained beforehand. None of the conventional approaches explicitly optimize the number of transitions for power reduction.…”

Section: Introductionmentioning

confidence: 99%

A practical gate resizing technique considering glitch reduction for low power design

Hashimoto

Onodera

Tamaru

1999

Proceedings of the 36th Annual ACM/IEEE Design Automation Conference

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We propose a method for power optimization that considers glitch reduction by gate sizing based on the statistical estimation of glitch transitions. Our method reduces not only the amount of capacitive and short-circuit power consumption but also the power dissipated by glitches which has not been exploited previously. The effect of our method is verified experimentally using 8 benchmark circuits with a 0.6 m standard cell library. Our method reduces the power dissipation from the minimum-sized circuits further by 9.8% on average and 23.0% maximum. We also verify that our method is effective under manufacturing variation.

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Power vs. delay in gate sizing: conflicting objectives?

Cited by 24 publications

References 9 publications

Feasible delay bound definition

Feasible delay bound definition

Delay-bound determination for path constraint satisfaction

A practical gate resizing technique considering glitch reduction for low power design

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