POWER2 fixed-point, data cache, and storage control units

Shippy, D.; Griffith, T. W.

doi:10.1147/rd.385.0503

Cited by 5 publications

(3 citation statements)

References 4 publications

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“…Floating-point instructions have a two-to-three-cycle pipeline delay; therefore, to keep both FPUs fully utilized, at least four independent floating-point instructions must be executing at the same time. (See [1][2][3] for details. )…”

Section: P0wer2 Cpu Considerationsmentioning

confidence: 99%

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Exploiting functional parallelism of POWER2 to design high-performance numerical algorithms

1994

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We describe the algorithms and architecture approach to produce high-performance codes for numerically intensive computations. In this approach, for a given computation, we design algorithms so that they perform optimally when run on a target machine-in this case, the new P0WER2™ machines from the RS/6000 family of RISC processors. The algorithmic features that we emphasize are functional parallelism, cache/register blocking, algorithmic prefetching, loop unrolling, and algorithmic restructuring. The architectural features of the P0WER2 machine that we describe and that lead to high performance are multiple functional units, high bandwidth between registers, cache, and memory, a large number of fixed-and floating-point registers, and a large cache and TLB (translation lookaside buffer). The paper gives two examples that illustrate how the algorithms and architectural features Interplay to produce high-performance codes. They are BLAS (basic linear algebra subroutines) and narrow-band matrix routines. These routines are included in ESSL (Engineering and Scientific Subroutine Library); an overview of ESSL is also given in the paper.

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Section: P0wer2 Cpu Considerationsmentioning

confidence: 99%

“…The new P0WER2™ workstations [1][2][3][4] of the RISC System/6000® (RS/6000) family of processors provide multiple fixed-point units (FXUs) and floating-point units (FPUs) which can work in parallel if there are no dependencies. We call this functional parallelism.…”

Section: Introductionmentioning

confidence: 99%

Exploiting functional parallelism of POWER2 to design high-performance numerical algorithms

1994

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“…The ICU does not request a translation until the ICU is sure that the dispatch stage will require the associated instruction. For a more detailed description of P0WER2 address translation, see the paper by Shippy and Griffith in this issue [1].…”

Section: Instruction Fetchingmentioning

confidence: 99%