POWER2: performance measurement and analysis of TPC-C

Fueled by higher clock rates and superscalar technologies, growth in processor speed continues to outpace improvement in memory system performance. Reflecting this trend, architects are developing increasingly complex memory hierarchies to mask the speed gap, compiler writers are adding locality enhancing transformations to better utilize complex memory hierarchies, and applications programmers are recoding their algorithm to exploit memory systems. All of these groups need empirical data on memory system behavior to guide their optimizations. This paper describes how to combine simple hardware support and sampling techniques to obtain such data without appreciably perturbing system performance. The idea is implemented in the Mprof prototype that projiles data stall cycles, first level cache misses, and second level misses on the Sun Sparc 10/41.

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POWER2: performance measurement and analysis of TPC-C

Cited by 4 publications

References 3 publications

Instruction cache performance of a commercial workload on the Motorola 88110 microprocessor

Instruction cache performance of a commercial workload on the Motorola 88110 microprocessor

POWER2: architecture and performance

Interrupt-based hardware support for profiling memory system performance

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