POWER4 system microarchitecture

Hou

2008 13th Asia-Pacific Computer Systems Architecture Conference

2008

Section: Figure 3 Data Path Of the Htm Designmentioning

confidence: 99%

Hardware transactional memory system for parallel programming

Hou

2008 13th Asia-Pacific Computer Systems Architecture Conference

2008

Advances in Computer Systems Architecture

“…The RAMpage model is based on the notion that DRAM, while still orders of magnitude faster than disk, is increasingly starting to display the attributes of a peripheral -that there is sufficient time to do other work while waiting for it [27] -particularly if relatively large units are moved between DRAM and the lowest SRAM level, a trend encouraged by the general trend towards higher-bandwidth interconnects [10,3] and larger cache block sizes (e.g., 512 bytes on the Power4 L3 cache [32]). …”

Section: The Rampage Approachmentioning

confidence: 99%

“…In critical word first, the word containing the reference which caused the miss is fetched first, followed by the rest of the block [13]. The Power4 has a variation of this, in which large cache blocks are divided into sectors, and the critical sector is fetched first [32]. Memory compression in effect reduces latency because a smaller amount of information must be moved on a miss.…”

Section: Alternativesmentioning

confidence: 99%

See 1 more Smart Citation

L1 Cache and TLB Enhancements to the RAMpage Memory Hierarchy

Machanick

Patel

2003

The RAMpage hierarchy moves main memory up a level to replace the lowest-level cache by an equivalent-sized SRAM main memory, and uses the TLB to cache page translations in that main memory. Earlier RAMpage evaluation used a relatively small L1 cache and TLB. For the RAMpage hierarchy, the effect of a small TLB is clearer than with a conventional hierarchy, because it is more feasible to make a TLB which maps a high fraction of main memory pages. This paper illustrates how more aggressive components higher in the memory hierarchy make time spent waiting for DRAM more significant as a fraction of total execution time, and, hence, approaches to hide the latency of DRAM become more important. For an instruction issue rate of 1 GHz, the simulated standard hierarchy waited for DRAM 10% of the time; with the instruction issue rate increased to 8 GHz, the fraction of time spent waiting for DRAM increased to 40%, and was higher for a larger L1 cache. The RAMpage hierarchy with context switches on misses was able to hide almost all DRAM latency. Increasing the processor speed in a standard hierarchy by a factor of 8 and increasing L1 cache size by a factor of 16, with DRAM speed unchanged, resulted in a speedup of 6.12. Adding the RAMpage model and introducing context switches on misses, with similar processor speed and L1 improvements, resulted in a speedup of 10.7 over the slowest conventional hierarchy, or 1.74 for the best case of the conventional hierarchy with the fastest processor. A larger TLB was shown to increase the viable range of RAMpage SRAM page sizes.

“…These chips containing multiple processor cores are denoted as on-chip multiprocessors (CMPs). Large scale systems, such as Piranha (1) and IBM Power4 (2) , combine multiple CMPs to obtain higher performance. The problem of choosing the appropriate architecture for implementing a CMP is still open nowadays.…”

Section: Introductionmentioning

confidence: 99%

Dense Gaussian Networks: Suitable Topologies for On-Chip Multiprocessors

Martínez

Vallejo

Beivide

et al. 2006

Int J Parallel Prog

This paper explores the suitability of dense circulant graphs of degree four for the design of on-chip interconnection networks. Networks based on these graphs reduce the Torus diameter in a factor √ 2 which translates into significant performance gains for unicast traffic. In addition, they are clearly superior to Tori when managing collective communications. This paper introduces a new two-dimensional node's labeling of the networks explored which simplifies their analysis and exploitation. In particular, it provides simple and optimal solutions to two important architectural issues: routing and broadcasting. Other implementation issues such as network folding and scalability by using hierarchical networks are also explored in this work.