2018
DOI: 10.1016/j.micpro.2018.07.007
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PowerTap: All-digital power meter modeling for run-time power monitoring

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Cited by 19 publications
(24 citation statements)
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References 26 publications
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“…As a future extension, we will investigate the possibility of running the method incrementally and on embedded multicores, coupling it with a real-time 3D reconstruction method [23] also accounting the energy constraints imposed by the computing platform [40,41]. We also plan to test the method with a wider dataset such as ScanNet ( [9]), by replacing the Multiboost algorithm, that failed to estimate a reasonable segmentation of ScanNet scenes, with a more sophisticated image segmentation algorithm based on neural networks.…”
Section: Discussionmentioning
confidence: 99%
“…As a future extension, we will investigate the possibility of running the method incrementally and on embedded multicores, coupling it with a real-time 3D reconstruction method [23] also accounting the energy constraints imposed by the computing platform [40,41]. We also plan to test the method with a wider dataset such as ScanNet ( [9]), by replacing the Multiboost algorithm, that failed to estimate a reasonable segmentation of ScanNet scenes, with a more sophisticated image segmentation algorithm based on neural networks.…”
Section: Discussionmentioning
confidence: 99%
“…In particular, their implementation minimizes the performance overhead typically associated with the software-implemented schemes that, unfortunately, compete with the other applications for the CPU. Hardware solutions can also increase the timing resolution of the entire monitoring system to efficiently manage faster physical phenomena [5], [6], [7]. Note that our proposal targets the design of a controller that leverages on the all-digital scheme proposed in [6] as the online power monitor whose detailed description is out of the scope of this research.…”
Section: Background and Related Workmentioning
confidence: 99%
“…Nevertheless, it can be detrimental for the performance of embedded platforms, since part of the computing resources must be devoted to the computation of both the power estimate and the control action. Recent investigations [5], [6], [7] proposed all-digital power monitoring solutions that estimate the consumed power from the switching activity of selected signals at the microarchitectural level. However, there is a complete absence of a unified and general methodology to control different energy related aspects, also considering applications and Operating System requirements.…”
Section: Introductionmentioning
confidence: 99%
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“…This approach combines power capping with coordinated dynamic voltage and frequency scaling (DVFS), data partitioning and core allocations for efficient use of both ARM processor and streaming accelerators on FPGA concurrently. A similar approach, leveraging a hardware implementation for the power capping, was proposed in [30,33], based on the modeling of DVFS and power gating actuators provided in [34]. A run-time task allocator for heterogeneous many-core platforms, SPARTA, was presented in [6].…”
Section: Ldpc Ifs Solution Id Processors Memoriesmentioning
confidence: 99%