2012 IEEE International Reliability Physics Symposium (IRPS) 2012
DOI: 10.1109/irps.2012.6241867
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Practical implications of chip-level statistical electromigration

Abstract: The accurate setting of electromigration (EM) design guidelines early is necessary to achieve chip-level fail goals. The issue is even more critical with the recognition of the percentage fail as a stochastic issue based on the individual EM elements. The challenge is the degree to fix those elements prior to the knowledge of chip-level fail rate. This paper will demonstrate a test case and approaches to early design guidelines which have shown success at meeting chip-level EM fail goals

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Cited by 4 publications
(1 citation statement)
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“…There are few papers that have studied full-chip level EM statistically [23], [24], or to have evaluated the impact of EM on performance of the circuits [25]. These works provide meaningful insights of the large-scale reliability evaluation, but their approaches do not focus on getting benefits from the EM modeling of specific interconnecting structures to the full-chip level.…”
Section: Em Of Full-chip 3-d Pdns With Msvsmentioning
confidence: 99%
“…There are few papers that have studied full-chip level EM statistically [23], [24], or to have evaluated the impact of EM on performance of the circuits [25]. These works provide meaningful insights of the large-scale reliability evaluation, but their approaches do not focus on getting benefits from the EM modeling of specific interconnecting structures to the full-chip level.…”
Section: Em Of Full-chip 3-d Pdns With Msvsmentioning
confidence: 99%