Practical metrics for evaluation of fault-tolerant logic design

Stempkovskiy, Alexander; Telpukhov, Dmitry; Solovyev, Roman; Balaka, Ekaterina; Naviner, Lírida Alves de Barros

doi:10.1109/eiconrus.2017.7910618

Cited by 2 publications

(2 citation statements)

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“…In [32], Han et al also construct a gate reliability model that derives approximate reliability results by bounding gate errors at much smaller time and space complexities than PTM. Upper and lower bounds are used in [33] to improve scalability as well, where they are used in the context of gate observability. The work of Rejimon and Bhanja [34] adopts Bayesian Networks to capture the dependencies among signals, constructing for each node of the network a function for the truth table of the gate including error probabilities.…”

Section: Background and Related Workmentioning

confidence: 99%

“…The first one is the lack of a framework capable of computing all three masking factors in a holistic way, which impacts the correctness of those works. The techniques presented in [31], [33], [37], [38] and [39] only take into account logical masking. On the other hand, approaches such as [15], [27], [40], [41] or [36] do not compute the electrical masking effect, while [42] and [2] overlook the logical masking effect.…”

Section: Background and Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Fast and Accurate SER Estimation for Large Combinational Blocks in Early Stages of the Design

Anglada

Canal

Aragón

et al. 2021

IEEE Trans. Sustain. Comput.

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Soft Error Rate (SER) estimation is an important challenge for integrated circuits because of the increased vulnerability brought by technology scaling. This paper presents a methodology to estimate in early stages of the design the susceptibility of combinational circuits to particle strikes. In the core of the framework lies MASkIt, a novel approach that combines signal probabilities with technology characterization to swiftly compute the logical, electrical, and timing masking effects of the circuit under study taking into account all input combinations and pulse widths at once. Signal probabilities are estimated applying a new hybrid approach that integrates heuristics along with selective simulation of reconvergent subnetworks. The experimental results validate our proposed technique, showing a speedup of two orders of magnitude in comparison with traditional fault injection estimation with an average estimation error of 5 percent. Finally, we analyze the vulnerability of the Decoder, Scheduler, ALU, and FPU of an out-of-order, superscalar processor design.

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Section: Background and Related Workmentioning

confidence: 99%