Practical Resource Management in Power-Constrained, High Performance Computing

Patki, Tapasya; Lowenthal, David K.; Sasidharan, Anjana; Maiterth, Matthias; Rountree, Barry; Schulz, Martin; Supinski, Bronis R. de

doi:10.1145/2749246.2749262

Cited by 74 publications

(47 citation statements)

References 45 publications

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“…For these reasons we generate our own cluster workload combining single-and multi-node applications, allowing us to measure the performance and power profiles of the workload. A similar methodology is used in other power and manufacturing variability related studies [16,44], but in our approach we use a wider number and range of applications.…”

Section: Methodology Evaluation 41 Experimental Setupmentioning

confidence: 99%

“…We extend the default behavior to not exceed the global power budget, by considering the worst case scenario, which is that each job can consume the maximum power budget allowed per socket. Additionally, we extend the scheduler to initiate backfilling for power as well [44]. Typically, if a job requests more sockets than currently available, the scheduler will try to schedule a different job without causing delays.…”

Section: Job Scheduling Policiesmentioning

confidence: 99%

“…For example, a few nodes may operate at full capacity, while the rest are disabled or constrained. Other approaches [40,44] take advantage of applications that can be considered moldable, meaning that these applications can run at different configurations (e.g. number of threads).…”

Section: Power-aware Budgeting and Schedulingmentioning

confidence: 99%

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Power efficient job scheduling by predicting the impact of processor manufacturing variability

Chasapis

Moretó

Schulz

et al. 2019

Proceedings of the ACM International Conference on Supercomputing

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Modern CPUs suffer from performance and power consumption variability due to the manufacturing process. As a result, systems that do not consider such variability caused by manufacturing issues lead to performance degradations and wasted power. In order to avoid such negative impact, users and system administrators must actively counteract any manufacturing variability. In this work we show that parallel systems benefit from taking into account the consequences of manufacturing variability when making scheduling decisions at the job scheduler level. We also show that it is possible to predict the impact of this variability on specific applications by using variabilityaware power prediction models. Based on these power models, we propose two job scheduling policies that consider the effects of manufacturing variability for each application and that ensure that power consumption stays under a systemwide power budget. We evaluate our policies under different power budgets and traffic scenarios, consisting of both singleand multi-node parallel applications, utilizing up to 4096 cores in total. We demonstrate that they decrease job turnaround time, compared to contemporary scheduling policies used on production clusters, up to 31% while saving up to 5.5% energy. CCS CONCEPTS • Computer systems organization → Parallel architectures; • Hardware → Power estimation and optimization;

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Section: Methodology Evaluation 41 Experimental Setupmentioning

confidence: 99%

Section: Job Scheduling Policiesmentioning

confidence: 99%

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Power efficient job scheduling by predicting the impact of processor manufacturing variability

Chasapis

Moretó

Schulz

et al. 2019

Proceedings of the ACM International Conference on Supercomputing

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“…Etinski et al [10,9] proposed the use of dynamic voltage and frequency scaling (DVFS) at the job scheduling-level to save energy and improve overall job performance. Patki et al [25] proposed power-aware backfilling to improve the throughput of the system. Ellsworth et al [8] presented a power scheduler that enforced a system-wide power bound by reallocating power across the cluster.…”

Section: Related Workmentioning

confidence: 99%

Power Tuning HPC Jobs on Power-Constrained Systems

Gholkar

Mueller

Rountree

2016

Proceedings of the 2016 International Conference on Parallel Architectures and Compilation

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As we approach the exascale era, power has become a primary bottleneck. The US Department of Energy has set a power constraint of 20MW on each exascale machine. To be able achieve one exaflop under this constraint, it is necessary that we use power intelligently to maximize performance under a power constraint. Most production-level parallel applications that run on a supercomputer are tightly-coupled parallel applications. A naïve approach of enforcing a power constraint for a parallel job would be to divide the job's power budget uniformly across all the processors. However, previous work has shown that a power capped job suffers from performance variation of otherwise identical processors leading to overall sub-optimal performance. We propose a 2-level hierarchical variation-aware approach of managing power at machinelevel. At the macro level, PPartition partitions a machine's power budget across jobs to assign a power budget to each job running on the system such that the machine never exceeds its power budget. At the micro level, PTune makes job-centric decisions by taking the performance variation into account. For every moldable job, PTune determines the optimal number of processors, the selection of processors and the distribution of the job's power budget across them, with the goal of maximizing the job's performance under its power budget. Experiments show that, at the micro level, PTune achieves a performance improvement of up to 29% compared to a naïve approach. PTune does not lead to any performance degradation, yet frees up almost 40% of the processors for the same performance as that of the naïve approach under a hard power bound. At the macro level, PPartition is able to achieve a throughput improvement of 5-35% compared to uniform power distribution.

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“…Most real HPC applications do not utilize the peak power allocated power-pernode, leading to inefcient use of both nodes and power. Thus, in average, applications utilize 70% or less of the provisioned power, which leads to an inevitable waste of not only power, but also performance and infrastructure, making clear that hardware solutions are not sufcient and improved software solutions are needed as well for power manage-ment [86,87]. Additionally, modern supercomputers consume an enormous amount of power, where a signicant fraction is dedicated to offer cooling capabilities considering the peak power provision of the whole infrastructure.…”

Section: Rate Monotonic Scheduling (Rms) and Earliest Deadline First mentioning

confidence: 99%

Memory-Aware Scheduling for Fixed Priority Hard Real-Time Computing Systems

Chaparro-Baquero¹

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Practical Resource Management in Power-Constrained, High Performance Computing

Cited by 74 publications

References 45 publications

Power efficient job scheduling by predicting the impact of processor manufacturing variability

Power efficient job scheduling by predicting the impact of processor manufacturing variability

Power Tuning HPC Jobs on Power-Constrained Systems

Memory-Aware Scheduling for Fixed Priority Hard Real-Time Computing Systems

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