Pre‐ and Postepitaxial Gettering of Oxidation and Epitaxial Stacking Faults in Silicon

Chen, M. C.; Silvestri, V. J.

doi:10.1149/1.2127428

Cited by 13 publications

(4 citation statements)

References 13 publications

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“…[1] are: 16.8, 18.4, 20, and 24 for nitride, polysilicon films, phosphorus diffusion, and control samples, respectively. This result shows that back-side gettering reduces the defective breakdown of the gate oxide (18)(19)(20)(21)(22), and the most effective technique is the 100 nm back-side nitride film.…”

Section: Resultsmentioning

confidence: 89%

“…Manuscript submitted April 29, 1988; revised manuscript received Nov. 28, 1988. This was in part Paper 616 presented at the Honolulu, HI, Meeting of the Society, Oct. [18][19][20][21][22][23] 1987.…”

Section: Acknowledgmentsmentioning

confidence: 99%

“…Much work has been done to improve the quality and reduce defect density of the as-grown oxide (15)(16)(17). The effects of other processing in CMOS technologies on the quality of the oxide has also been a subject of intensive study; for example, intrinsic and extrinsic gettering in the front-end processing (18)(19)(20)(21)(22), high-temperature treatments after gate polysilicon deposition (15,(23)(24)(25), reactive ion etching (26)(27)(28)(29), ion implantation and annealing (14,30), postmetal annealing (31), and final passivation film deposition (32). However, most of the studies concerning the breakdown phenomenon in silicon dioxide have employed simple, minimally processed MOS capacitors.…”

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confidence: 99%

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Breakdown Yield and Lifetime of Thin Gate Oxides in CMOS Processing

Koyanagi

Holland

et al. 1989

J. Electrochem. Soc.

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The processing effects on thin gate oxide yield and lifetime were studied by using ramp voltage and time-dependent dielectric breakdown (TDDB) measurements on minimally processed MOS capacitors and fully processed devices in a CMOS technology. Gate oxides grown in a wet ambient are considerably superior to those grown in a dry 02 ambient interms of breakdown distribution, yield, and lifetime. In addition, the correlation between lifetime and applied electric field also suggests an advantage for using wet oxides rather than dry oxides for scaling down the thickness. Several processing modules in a CMOS technology on the gate oxide breakdown characteristics are examined. High temperature oxidatiqn and drive or back-side gettering processing prior to the gate oxidation steps improve the oxide yield. Reactive ion or plasma etching for the gate electrode definition reduces lifetime of approximately 10% of the devices compared to the wet-etched control. However, the most significant influence on the gate oxide yield and lifetime occurs during the oxidation and polysilicon gate deposition processing steps. Fully processed CMOS devices show a large reduction in gate oxide yield and lifetime as compared to minimally processed capacitors. Additional processing for double level meta]lization further degrades the gate oxide. This result indicates the cumulative nature of processing induced damage. Breakdown characteristics are significantly degraded when electrons are injected from the polysilicon gate as opposed to injection from the silicon substrate for the fully processed devices. This polarity dependence can be explained by plasma processing induced trapped holes near the polysilicon/SiO2 interface which also cause anomalous leakage currents with a negative gate bias.

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Section: Resultsmentioning

confidence: 89%

Section: Acknowledgmentsmentioning

confidence: 99%

mentioning

confidence: 99%

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Breakdown Yield and Lifetime of Thin Gate Oxides in CMOS Processing

Koyanagi

Holland

et al. 1989

J. Electrochem. Soc.

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“…In the 1970s, SiN x films fabricated by low-pressure chemical vapor-deposition (LPCVD), which were deposited on the backside of Si wafers, were reported to reduce the subsequent oxidation-induced stacking faults on the front side via a pre-oxidation anneal at 1000–1200 °C, which was believed to be due to gettering. − The mechanisms were speculated to be strain-induced gettering and/or gettering assisted by point defects from annealing with non-stoichiometric silicon nitride films . Another observation was that the crystallization of β-Si 3 N 4 during pre-annealing at 1000 °C can develop local stress at the Si surface, and this stress then relaxes during subsequent oxidation (above 1000 °C), resulting in the generation of dislocations which act as sinks for metallic impurities .…”

Section: Introductionmentioning

confidence: 99%

Impurity Gettering by Silicon Nitride Films: Kinetics, Mechanisms, and Simulation

Hameiri

Truong

et al. 2021

ACS Appl. Energy Mater.

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Metallic impurities in the silicon wafer bulk are one of the major efficiency-limiting factors in silicon solar cells. Gettering can be used to significantly lower the metal concentrations. Although gettering by silicon nitride films has been reported in literature, much remains unknown about its gettering behaviors and mechanisms. In this study, the gettering kinetics and mechanisms of silicon nitride films, from both plasma-enhanced chemical vapor deposition (PECVD) and low-pressure chemical vapor deposition (LPCVD), are investigated. By monitoring the kinetics of iron loss from the silicon wafer bulk, it is confirmed that silicon nitride gettering takes place mainly via segregation, even at a low annealing temperature of 400 °C. Simulation of the gettering kinetics suggests the presence of an interfacial diffusion barrier in some cases, which slows down the transport of iron impurities from the silicon wafer bulk to the silicon nitride gettering regions. The activation energy of the segregation gettering process is estimated to be 0.9 ± 0.1 eV for the investigated PECVD silicon nitride film at 400–900 °C and 1.6 ± 0.5 eV for the investigated LPCVD silicon nitride film at 400–700 °C.

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Thin silicon epitaxial layers on preannealed silicon substrates

Weidner¹,

Kirscht²,

Richter³

et al. 1987

Cryst. Res. Technol.

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Multistep-temperature pretreatment is used to create defect denuded zoncs a t surfaces in conjunction with bulk defects in oxygen rich substrate wafers. Using structural ctching, RF-CV measurements, EBIC investigations, and gamma spectroscopy i t is shown t h a t bulk defects act as sinks for metallic impurities being fixed at a n early stage of bipolar technology, already Etchable defects induced due to subsequent processing stepse.g., emerging irom bulk regions and entering denuded zones -contain less metallic impurities. 2 pm epitaxial layers deposited on such substrates with bulk defects and denuded zones reveal excellent structural and electrical properties.Eine mehrstufige Wiirmebehandlung von sauerstoffreichen Substraten fuhrt im oberfliivhennahen Bereich des Substrates zu defektverarinten Zonen und zu Kristalldefekten iiii Volumen. Mit Atzuntersuchungen, RF-CV-Messungen, EBIC-Untersuehungen untl G~iiimaspektroskopie wird gezeigt, daB die Volumen-Kristalldefekte als Senke fur metallische Verunreinigungen wirken, wobei diese bereits in einem friiheii Stadium einer BipolarTeclinologie an den Defekten fixiert werden. Im spateren Verlauf hinzugekomniene oder die verarmte Zone erreichende Defekte enthalten weniger metallische Verunreinigungen. 2 pi-Epitaxieschichten auf solchen Substraten mit Volumen-Kristalldefekten und einrr drfektverarmten Zone a n der Oberflache des Substrates haben sehr gute strukturelle und elcktrischt Eigcnschaften.

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Pre‐ and Postepitaxial Gettering of Oxidation and Epitaxial Stacking Faults in Silicon

Cited by 13 publications

References 13 publications

Breakdown Yield and Lifetime of Thin Gate Oxides in CMOS Processing

Breakdown Yield and Lifetime of Thin Gate Oxides in CMOS Processing

Impurity Gettering by Silicon Nitride Films: Kinetics, Mechanisms, and Simulation

Thin silicon epitaxial layers on preannealed silicon substrates

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