1998 IEEE International Joint Conference on Neural Networks Proceedings. IEEE World Congress on Computational Intelligence (Cat
DOI: 10.1109/ijcnn.1998.682327
|View full text |Cite
|
Sign up to set email alerts
|

Precision improvement in current-mode winner-take-all circuits using gain-boosted regulated-cascode CMOS stages

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...

Citation Types

0
9
0

Publication Types

Select...
4
1

Relationship

0
5

Authors

Journals

citations
Cited by 8 publications
(9 citation statements)
references
References 4 publications
0
9
0
Order By: Relevance
“…An interesting and efficient, yet very simple, alternative to the WTA original circuit [4] is the one proposed by Sekerkiran et al in [5]. Using a gain-boosted regulatedcascode configuration composed of transistors MP1, MP2 and MP3, and current source IPol, the impedance at WTAout node is highly increased.…”
mentioning
confidence: 98%
See 4 more Smart Citations
“…An interesting and efficient, yet very simple, alternative to the WTA original circuit [4] is the one proposed by Sekerkiran et al in [5]. Using a gain-boosted regulatedcascode configuration composed of transistors MP1, MP2 and MP3, and current source IPol, the impedance at WTAout node is highly increased.…”
mentioning
confidence: 98%
“…In a matrix organised cell core, simultaneous vertical and horizontal inhibition signals are propagated when the first winning cell is found so that only one single digital output is in high state pinpointing a single global winner. Using the analogue WTA circuit proposed in [5] implemented in 0.35 mm CMOS technology, resolutions as high as 10 nA can be achieved, and together with the proposed digital logic a single winner can be obtained every 1 ms time interval. The simulated matrix could be used as the core for the VLSI implementation of an SCD strategy in a neuromorphic vision chip [2].…”
mentioning
confidence: 98%
See 3 more Smart Citations