A high-precision high-resolution WTA-MAX circuit of O(N) complexity

Aksin, Devrim Yılmaz

doi:10.1109/82.996058

Cited by 12 publications

(6 citation statements)

References 25 publications

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“…The average in the 15 15 square can be computed with a similar multistep operation: one linear convolution and 24 shifts of three pixels each, for a total of 73 additional steps. The maximum line average can be determined by a winner-take-all (WTA) circuit [14], [15]. Taking into account the rather small number of inputs (twelve), the existing chips allow high speed and precision.…”

Section: B Shifting Strategymentioning

confidence: 99%

Cellular Neural Networks With Virtual Template Expansion for Retinal Vessel Segmentation

Perfetti

Ricci

Casali

et al. 2007

IEEE Trans. Circuits Syst. II

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A retinal vessel segmentation method based on cellular neural networks (CNNs) is proposed. The CNN design is characterized by a virtual template expansion obtained through a multistep operation. It is based on linear space-invariant 3 3 templates and can be realized using existing chip prototypes like the ACE16K. The proposed design is capable of performing vessel segmentation within a short computation time. It was tested on a publicly available database of color images of the retina, using receiver operating characteristic curves. The simulation results show good performance comparable with that of the best existing methods.

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Section: B Shifting Strategymentioning

confidence: 99%

Cellular Neural Networks With Virtual Template Expansion for Retinal Vessel Segmentation

Perfetti

Ricci

Casali

et al. 2007

IEEE Trans. Circuits Syst. II

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“…The proposed architecture also can apply to applications which perform specific operations on k targets found within the input set. As compared to architectures in [ 12 , 32 ] and [ 33 ] for the k NN application, the proposed architecture takes advantage of the pipeline fashion to have higher throughput even though these architectures have same latency of picking out k winners.…”

Section: Resultsmentioning

confidence: 99%

Efficient k-Winner-Take-All Competitive Learning Hardware Architecture for On-Chip Learning

Hwang

2012

Sensors

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A novel k-winners-take-all (k-WTA) competitive learning (CL) hardware architecture is presented for on-chip learning in this paper. The architecture is based on an efficient pipeline allowing k-WTA competition processes associated with different training vectors to be performed concurrently. The pipeline architecture employs a novel codeword swapping scheme so that neurons failing the competition for a training vector are immediately available for the competitions for the subsequent training vectors. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for realtime on-chip learning. Experimental results show that the SOPC has significantly lower training time than that of other k-WTA CL counterparts operating with or without hardware support.

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“…Increasing the number of inputs does not a the accuracy of BT topologies. Nevertheless, the area, power, and delay are increa During the 90′s decade, binary-tree WTAs were used widely in applications such as linear filters, analog-to-digital converters, vector quantizers, and fuzzy circuits [2,4,6 The voltage-mode binary-tree WTA in Figure 11 is presented In [17]. The initial com son is fulfilled between two random inputs.…”

Section: Binary Tree Wta Circuitsmentioning

confidence: 99%

Winner-Take-All and Loser-Take-All Circuits: Architectures, Applications and Analytical Comparison

Rahiminejad,

Aminzadeh

2023

Chips

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A high-precision high-resolution WTA-MAX circuit of O(N) complexity

Cited by 12 publications

References 25 publications

Cellular Neural Networks With Virtual Template Expansion for Retinal Vessel Segmentation

Cellular Neural Networks With Virtual Template Expansion for Retinal Vessel Segmentation

Efficient k-Winner-Take-All Competitive Learning Hardware Architecture for On-Chip Learning

Winner-Take-All and Loser-Take-All Circuits: Architectures, Applications and Analytical Comparison

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