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2005) Iterative optimization for joint design of source and channel codes using genetic algorithms, Journal of the Chinese Institute of Engineers, 28:5, 803-810, ABSTRACTThis paper presents a novel algorithm for the joint design of source and channel codes. In the algorithm, channel-optimized vector quantization (COVQ) and rate-punctured convolutional coding (RCPC) are used for design of the source code and the channel code, respectively. We employ the genetic algorithm (GA) to prevent the design of COVQ from falling into a poor local optimum. We also adopt the GA to reduce the computational time needed for realizing the unequal error protection scheme best matched to the COVQ. Both the GA-based source coding and channel coding scheme are then iteratively combined to achieve a near global optimal solution for the joint design. Numerical results show that the algorithm can be an effective alternative for applications where high rate-distortion performance and low computational complexity are desired.

A novel JPEG2000-based algorithm, termed quality pre-specifiable layered JPEG2000 (QPSL-JPEG2000), for realizing a layered image transmission (LIT) system is presented in this paper. In the QPSL-JPEG2000 algorithm, the resolution and rate associated with each layer of the LIT system can be pre-specified. It encodes an image one layer at a time using the modified JPEG2000 technique. The encoding process at each layer only covers the subbands having resolution level lower than the designated resolution at that layer subject to the pre-specified incremental rate budget. The encoding results at the previous layers will be used in the current layer to accelerate the encoding process. Numerical results show that the QPSL-JPEG2000 algorithm outperforms its counterparts for constructing the rate and resolution pre-specified LIT systems.

A novel k-winners-take-all (k-WTA) competitive learning (CL) hardware architecture is presented for on-chip learning in this paper. The architecture is based on an efficient pipeline allowing k-WTA competition processes associated with different training vectors to be performed concurrently. The pipeline architecture employs a novel codeword swapping scheme so that neurons failing the competition for a training vector are immediately available for the competitions for the subsequent training vectors. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for realtime on-chip learning. Experimental results show that the SOPC has significantly lower training time than that of other k-WTA CL counterparts operating with or without hardware support.

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