Efficient k-Winner-Take-All Competitive Learning Hardware Architecture for On-Chip Learning

Abstract

A novel k-winners-take-all (k-WTA) competitive learning (CL) hardware architecture is presented for on-chip learning in this paper. The architecture is based on an efficient pipeline allowing k-WTA competition processes associated with different training vectors to be performed concurrently. The pipeline architecture employs a novel codeword swapping scheme so that neurons failing the competition for a training vector are immediately available for the competitions for the subsequent training vectors. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for realtime on-chip learning. Experimental results show that the SOPC has significantly lower training time than that of other k-WTA CL counterparts operating with or without hardware support.

Bio-Inspired Techniques in a Fully Digital Approach for Lifelong Learning

“…Due to their useful characteristics, WTA networks have been modeled by a computational point of view (Oster et al, 2009) and successively implemented in hardware CMOS (Chicca et al, 2014), with memristive devices (Ambrogio et al, 2016) and realizing digital designs in FPGAs (Ou et al, 2012).…”