Predicting Serializability Violations: SMT-Based Search vs. DPOR-Based Search

Sinha, Arnab; Malik, Sharad; Wang, Chao; Gupta, Aarti

doi:10.1007/978-3-642-34188-5_11

Cited by 13 publications

(2 citation statements)

References 26 publications

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“…In the context of systematic testing, often based on stateless model checking [22,25,64] or predictive analysis [33,54,56,57,62,63], a number of methods have been proposed to handle weak memory such as TSO/PSO [1,16,34,67], PowerPC [2], and C++11 [51,52]. However, since they rely on concretely executing the program, and require the user to provide test inputs, they can only be used to detect bugs.…”

Section: Related Workmentioning

confidence: 99%

Thread-modular static analysis for relaxed memory models

Kusano

Wang

2017

Proceedings of the 2017 11th Joint Meeting on Foundations of Software Engineering

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We propose a memory-model-aware static program analysis method for accurately analyzing the behavior of concurrent software running on processors with weak consistency models such as x86-TSO, SPARC-PSO, and SPARC-RMO. At the center of our method is a unified framework for deciding the feasibility of inter-thread interferences to avoid propagating spurious data flows during static analysis and thus boost the performance of the static analyzer. We formulate the checking of interference feasibility as a set of Datalog rules which are both efficiently solvable and general enough to capture a range of hardware-level memory models. Compared to existing techniques, our method can significantly reduce the number of bogus alarms as well as unsound proofs. We implemented the method and evaluated it on a large set of multithreaded C programs. Our experiments show the method significantly outperforms state-of-the-art techniques in terms of accuracy with only moderate runtime overhead.

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Section: Related Workmentioning

confidence: 99%

Thread-modular static analysis for relaxed memory models

Kusano

Wang

2017

Proceedings of the 2017 11th Joint Meeting on Foundations of Software Engineering

Self Cite

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“…While in other uses of serializability the transactions are sequential, in our case a single invocation of an event handler consists of several asynchronous procedures that can interleave arbitrarily in between them. Farzan and Madhusudan [15,16] and Bouajjani et al [10] investigate decision procedures for conflict serializability of finitestate concurrent models while checking serializability in general has been approached using both static, e.g., [18,20,32,34], and dynamic tools, e.g., [17,33,19,30].…”

Section: Related Workmentioning

confidence: 99%

Verifying Robustness of Event-Driven Asynchronous Programs Against Concurrency

Bouajjani

Emmi

Enea

et al. 2017

Programming Languages and Systems

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We define a correctness criterion, called robustness against concurrency, for a class of event-driven asynchronous programs that are at the basis of modern UI frameworks in Android, iOS, and Javascript. A program is robust when all possible behaviors admitted by the program under arbitrary procedure and event interleavings are admitted even if asynchronous procedures (respectively, events) are assumed to execute serially, one after the other, accessing shared memory in isolation. We characterize robustness as a conjunction of two correctness criteria: event-serializability (i.e., events can be seen as atomic) and event-determinism (executions within each event are insensitive to the interleavings between concurrent tasks dynamically spawned by the event). Then, we provide efficient algorithms for checking these two criteria based on polynomial reductions to reachability problems in sequential programs. This result is surprising because it allows to avoid explicit handling of all concurrent executions in the analysis, which leads to an important gain in complexity. We demonstrate via case studies on Android apps that the typical mistakes programmers make are captured as robustness violations, and that violations can be detected efficiently using our approach.

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Symbolic Predictive Cache Analysis for Out-of-Order Execution

Huang

Wang

2022

Fundamental Approaches to Software Engineering

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We propose a trace-based symbolic method for analyzing cache side channels of a program under a CPU-level optimization called out-of-order execution (OOE). The method is predictive in that it takes the in-order execution trace as input and then analyzes all possible out-of-order executions of the same set of instructions to check if any of them leaks sensitive information of the program. The method has two important properties. The first one is accurately analyzing cache behaviors of the program execution under OOE, which is largely overlooked by existing methods for side-channel verification. The second one is efficiently analyzing the cache behaviors using an SMT solver based symbolic technique, to avoid explicitly enumerating a large number of out-of-order executions. Our experimental evaluation on C programs that implement cryptographic algorithms shows that the symbolic method is effective in detecting OOE-related leaks and, at the same time, is significantly more scalable than explicit enumeration.

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Predicting Serializability Violations: SMT-Based Search vs. DPOR-Based Search

Cited by 13 publications

References 26 publications

Thread-modular static analysis for relaxed memory models

Thread-modular static analysis for relaxed memory models

Verifying Robustness of Event-Driven Asynchronous Programs Against Concurrency

Symbolic Predictive Cache Analysis for Out-of-Order Execution

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