Prediction-based flow control for network-on-chip traffic

Ogras,; Marculescu, Diana

doi:10.1109/dac.2006.229272

Cited by 17 publications

(17 citation statements)

References 12 publications

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“…In [19], a prediction-based flow-control strategy for onchip networks is proposed where each router predicts future buffer fillings to detect future congestion problems. The buffer filling predictions are based on a router model.…”

Section: Related Workmentioning

confidence: 99%

Congestion-Controlled Best-Effort Communication for Networks-on-Chip

Brand¹,

Ciordas²,

Goossens³

et al. 2007

2007 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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Congestion has negative effects on network performance. In this paper, a novel congestion control strategy is presented for Networks-on-Chip (NoC). For this purpose we introduce a new communication service, congestioncontrolled best-effort (CCBE). The load offered to a CCBE connection is controlled based on congestion measurements in the NoC. Link utilization is monitored as a congestion measure, and transported to a Model Predictive Controller (MPC). Guaranteed bandwidth and latency connections in the NoC are used for this, to assure progress of link utilization data in a congested NoC. We also present a simple but effective model for link utilization for the model-based predictions. Experimental results show that the presented strategy is effective and has reaction speeds of several microseconds which is considered acceptable for realtime embedded systems.

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Section: Related Workmentioning

confidence: 99%

Congestion-Controlled Best-Effort Communication for Networks-on-Chip

Brand¹,

Ciordas²,

Goossens³

et al. 2007

2007 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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show abstract

“…Traditionally, network research has been focused on directly computing the router delay [14,15]. A state space representation of an NoC router driven by stochastic inputs is proposed in [16]. Link utilization is monitored as a congestion measure, and transported to a model predictive controller (MPC).…”

Section: Literature Review and Proposed Ideamentioning

confidence: 99%

State observer controller design for packets flow control in networks-on-chip

Sehgal

Chauhan

2009

J Supercomput

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Packet-switched networks-on-chips (NoCs) are efficient communication architectures for future multiprocessors system-on-chip (MP-SoC) platforms. However the run-time management of their communication, especially flow control from individual intellectual property (IP) in an NoC which contains large number of IPs, is a challenging task. This paper proposes a state space model for NoC with state observer controller in its feedback path. It is seen that controlling the input and output flow rates alone is not sufficient to stabilize the network, but it is also important to monitor the intermediate flow rates from the on-chip routers. This is possible through a state space model for the NoC. The state observer observes the flow rates from each on-chip router which are then treated as state space variables. These variables can be controlled by the poles placement in the feedback controller. The proposed mathematical model can also observe the required intermediate flow rates which cannot be measured directly (reduced state observer). With these observed states we can attach a state controller. With this controller the network can be stabilized by controlling the flow rates at the intermediate level.State observer controller design for packets flow control 299

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“…Here we use two typical examples to explain the reason. In the 1 st example (the combination of monitoring and injection rate adjustment techniques), monitors collect link utilization values, the number of packets buffered or other congestion metrics for regulating output traffic rates of cores [20,21,24]. However, a congestion controller controls generating subsequent packets rather than routing packets which have suffered congestion.…”

Section: Introductionmentioning

confidence: 99%

Monitoring and timing prediction in early analyzing and checking performance of interconnection networks at ESL

Wang

Yeh

2012

Thirteenth International Symposium on Quality Electronic Design (ISQED)

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When an advanced interconnection architecture with many routers (or switches) is designed to integrate a large number of system components into a single chip, its performance has to be analyzed or verified. This will take considerable time if no cost-effective technique is developed to deal with the complex task. In the paper, we present an early timing checking technique to verify interconnection performance at electronic system level. Experimental results show that the proposed technique has better violation detection efficiency than other ones.

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Prediction-based flow control for network-on-chip traffic

Cited by 17 publications

References 12 publications

Congestion-Controlled Best-Effort Communication for Networks-on-Chip

Congestion-Controlled Best-Effort Communication for Networks-on-Chip

State observer controller design for packets flow control in networks-on-chip

Monitoring and timing prediction in early analyzing and checking performance of interconnection networks at ESL

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