Prediction of Charged Device Model Peak Discharge Current for Microelectronic Components

Shukla, Vrashank; Boselli, Gianluca; Dissegna, Mariano; Duvvury, C.; Sankaralingam, Raj; Rosenbaum, Elyse

doi:10.1109/tdmr.2014.2342241

Cited by 7 publications

(2 citation statements)

References 10 publications

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“…While standardized field-induced CDM (FICDM) is the default CDM testing/stress method [12,23], transmission line pulsing (TLP) IV characterization reports have also been used for CDM purposes [17,23] Previous works show a variety of different methods to try to overcome the issues caused by CDM. Some findings argue the importance of the packaging on CDM occurrence (pin count, die area, metal frame structure [24]) by presenting their findings in terms of CDM peak currents dependence of various packages [18,23,27] or by trying to model the package parameters into software scripts to be used during pre-silicon testing simulation steps [15,20,26]. Similarly, a number of previously published works discuss the possibility of full-chip simulations [10,[16][17][18].…”

Section: Introductionmentioning

confidence: 99%

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CDM Protection Test Structure for I/O Cells in a Submicronic Technology

Dobre

Coll²,

Brezeanu

2021

Electronics

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This paper proposes an investigation of a CDM (charge device model) electrostatic discharge (ESD) protection method used in submicronic input–output (I/O) structures. The modeling of the commonly used ESD protection devices as well as the modeling of the breakdown caused by ESD is not accurate using traditional commercial tools, hence the need for test-chip implementation, whenever a new technology node is used in production. The proposed method involves defining, implementing, testing, and concluding on one test-chip structure named generically “CDM ground resistance”. The structure assesses the maximum ground resistance allowed for the considered technology for which CDM protection is assured. The findings are important because they will be actively used as CDM protection for all I/O structures developed in the considered submicronic technology node. The paper will conclude on the constraints in terms of maximum resistance of ground metal track allowed to be CDM protected.

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Section: Introductionmentioning

confidence: 99%

“…Most of the studies cited above related to different research area around CDM phenomena have a thing in common: they highlight the importance of the parasitic ground bus resistance in the CDM modeling process [13,[16][17][18].…”

Section: Introductionmentioning

confidence: 99%