Predictive Line Buffer: A Fast, Energy Efficient Cache Architecture

Ali, Kashif; Aboelaze, Mokhtar; Datta, Samir

doi:10.1109/second.2006.1629366

Cited by 3 publications

(5 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…With the development of integrated circuit, the embedded processor has been applied in more and more power-constrained environment. The low power method of cache has attracted much attention in processor design in recent years [2][3][4][5][6][7][8][9][10].…”

Section: Introductionmentioning

confidence: 99%

“…Several prediction techniques were carried out to guarantee the hit ratio in follow-up researches [5][6][7][8]. There are also some other low power designs derived from the filter cache, such as line buffer cache [9] which has the same principle as filter cache but limited the size of filter the one cache line size. In a word, the filter cache has been deeply studied as the low power cache structure in the signal core processor and it has been successfully applied to commercial processors [10,11].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

An Energy Efficient Cache Design for Multi-core Processors

Cao

Zhang

2013

2013 IEEE International Conference on Green Computing and Communications and IEEE Internet of Things and IEEE Cyber, Physical A

View full text Add to dashboard Cite

Multi-core processors have become the main development trend of processor, because of their advantages of performance and power dissipation. The multi-core structure leads to many new features for on-chip memory system, such as much larger capacity of cache, more complex circuit for cache sharing management of different threads. The low power issue is still a big deal for multi-core processors, since more and more application environment is power-constrained. To deal with the new challenge of energy efficient cache design for multi-core processors, we extend the low power cache design filter cache" which has been widely used in single core processor to the multi-core structure. A public-filter is inserted at level-0 as the first instruction source for all the cores and a dynamic management method is also applied for the public-filter. It can dynamically allocate the public-filter for each core by the runtime filter hit ratio. The experiment results show that the presented method can save about 29% energy and almost has no performance loss.

show abstract

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

An Energy Efficient Cache Design for Multi-core Processors

Cao

Zhang

2013

2013 IEEE International Conference on Green Computing and Communications and IEEE Internet of Things and IEEE Cyber, Physical A

View full text Add to dashboard Cite

show abstract

“…In this paper, we extended our single predictive-line buffer scheme (proposed in [2]) in order to capture long loops in the line buffers. We presented a cache architecture that utilizes 4-8 line buffers, the BTB and a simple prediction mechanism to reduce the energy consumption in the instruction cache.…”

Section: Discussionmentioning

confidence: 99%

“…(Fig. 2 and 1 In [2] we showed how to use a single line buffer in order to reduce energy consumption in a direct-mapped cache. While 16-instruction loops cannot be be captured using a single line buffer, they could be captured if 4-8 line buffers are used with a good cache organization to guarantee that the instructions in the loops are mapped to the entire set of line buffers instead of replacing each other in a small number of line buffers.…”

Section: Motivationmentioning

confidence: 99%

See 1 more Smart Citation

Reducing Energy in Instruction Caches by Using Multiple Line Buffers with Prediction

Ali

Aboelaze

Datta

High-Performance Computing

View full text Add to dashboard Cite

Abstract-Energy efficiency plays a crucial role in the design of embedded processors especially for portable devices with its limited energy source in the form of batteries. Since memory access (either cache or main memory) consumes a significant portion of the energy of a processor, the design of fast low-energy caches has become a very important aspect of modern processor design. In this paper, we present a novel cache architecture for reduced energy instruction caches. Our proposed cache architecture consists of the L1 cache, multiple line buffers, and a prediction mechanism to predict which line buffer, or L1 cache to access next. We used simulation to evaluate our proposed architecture and compare it with the HotSpot cache, Filter cache, Predictive line buffer cache and Way-Halting cache. Simulation results show that our approach can reduce instruction cache energy consumption, on average, by 75% (compared to the base line architcture) without sacrificing performance I. INTRODUCTION On-chip caches can have a huge impact on the processor speed. Caches are faster than the main memory, and consume less power per access than the main memory. A well-designed cache results in a fast and energy efficient processor.As the size of the chip increases, and the number of transistors on the chip increases, the cache size also increases, for the DEC 21164 processor, 43% of the total energy consumed in the chip is consumed by the cache [3]. Therefore, reducing energy consumption in caches is a priority in the design of embedded processors. In the rest of this section, we briefly review some of the previous attempts to reduce instruction cache energy in embedded processors.In [8] the authors showed how to use a unified cache to reduce the total area of the cache by 20-30% and maintain the same hit rate as a split cache. Albonesi in [1] proposed the selective way cache. In the selective way cache, preferred ways (a subset of all the ways) are accessed first; in case of a miss, the rest of the ways are accessed. The savings in energy (by not accessing all the ways) is accomplished at the expense of increasing the access time (2 cycles to access the cache in the case of misprediction). Zhang et al [13] proposed a cache where by setting a configuration register they can reconfigure the cache size, the cache associativity, and the cache line size. By fine-tuning the cache parameters to the application, they achieved a power saving of up to 40%.Way prediction was used in [14] to reduce cache energy. In order not to sacrifice the cache speed, they used a 2-level prediction scheme. First, they decide if they use way

show abstract