Predictive Successive Approximation ADC

Mitrovic, Jovan; Zhang, Yiqiao; Ignjatović, Željko

doi:10.1109/iscas.2018.8351230

Cited by 3 publications

(1 citation statement)

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“…For given ADC specifications, the analysis obtains the frequency range of RSw mode and finds the optimum number of bit‐cycles to skip during consecutive conversions. Unlike predictive designs, which extract information from previous bits [14, 18, 20, 21], no additional prediction logic or error checking and correction circuitries are required to implement the proposed analogue‐to‐digital (A‐to‐D) algorithm. Although analytical formulation presented in this paper is generic, a 10 bit, 104 kS/s ADC is designed to show circuit‐level realisation of the RSw mode A‐to‐D algorithm.…”

Section: Introductionmentioning

confidence: 99%

Reduced switching mode for SAR ADCs: analysis and design of SAR A‐to‐D algorithm with periodic standby mode circuit components

Joshi

Shrimali

Sharma

2020

IET Circuits, Devices & Systems

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This study presents the analysis and design of reduced switching (RSw) activity mode successive approximation register (SAR) analogue-to-digital (A-to-D) algorithm. For given analogue-to-digital converter (ADC) specifications, RSw mode design is based on the observation that the signal variation in two successive samples becomes linear over a certain range of input frequencies. Hence, dispensable switching activity between the two samples can be eliminated by enabling periodic temporal reference to the converter. No prediction or logic circuitry is required to extract information from previous bits. However, there exists a trade-off between the input frequency and the sampling frequency. A design criterion is derived using numerical mathematics to skip evaluation of the optimum number of bits while maintaining the desired signal-to-noise and distortion ratio. The design criterion is validated through behavioural simulations using MATLAB/Simulink ®. Furthermore, a fully differential 10bit, 104 kS/s ADC is designed in a standard 180 nm CMOS technology to demonstrate circuit implementation of the RSw mode. In the RSw mode, power dissipation in the comparator and relevant digital circuitry decreases by 20%. The ADC achieves lowfrequency effective number of bits of 9.7 bits and spurious free dynamic range of 68.3 dB. With 1.8 V supply voltage, average power dissipation in the core ADC is 2.54 μW; resulting in figure-of-merit of 29.3 fJ/conv-step.

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