Preemptive Hardware Multitasking in ReconOS

Happe, Markus; Traber, Andreas; Keller, Ariane

doi:10.1007/978-3-319-16214-0_7

Cited by 42 publications

(19 citation statements)

References 8 publications

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“…This is because the state may be spread out across Flip-Flops, Logic Cells and BRAMs. Saving and restoring the complete state for such a case can easily take anywhere from microseconds to milliseconds [69] in addition to partial reconfiguration latency. Further, the hardware support required for a preemptable hardware module tends to be rather restrictive and very target specific.…”

Section: Schedulingmentioning

confidence: 99%

A Survey on FPGA Virtualization

Vaishnav

Pham

Koch

2018

2018 28th International Conference on Field Programmable Logic and Applications (FPL)

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FPGA accelerators are being applied in various types of systems ranging from embedded systems to cloud computing for their high performance and energy efficiency. Given the scale of deployment, there is a need for efficient application development, resource management, and scalable systems, which make FPGA virtualization extremely important. Consequently, FPGA virtualization methods and hardware infrastructures have frequently been proposed in both academia and industry for addressing multi-tenancy execution, multi-FPGA acceleration, flexibility, resource management and security. In this survey, we identify and classify the various techniques and approaches into three main categories: 1) Resource level, 2) Node level, and 3) Multi-node level. In addition, we identify current trends and developments and highlight important future directions for FPGA virtualization which require further work.

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Section: Schedulingmentioning

confidence: 99%

A Survey on FPGA Virtualization

Vaishnav

Pham

Koch

2018

2018 28th International Conference on Field Programmable Logic and Applications (FPL)

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“…Scheduling is the key to multi-tenancy, but the conventional techniques (preemptive, non-preemptive, and cooperative) cannot be used for FPGA accelerators unchanged, as the state of the system that needs to be saved and restored is not trivial. The state data may be distributed across all different resources on FPGA fabric and one single operation to save or restore the state can add micro to milli seconds to the latency [98]. However, the requirement of mandatory dedicated hardware module can be avoided, as in [99], where such jobs are either blocked or sent back to CPU to perform.…”

Section: Schedulingmentioning

confidence: 99%

Revisiting the High-Performance Reconfigurable Computing for Future Datacenters

2020

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Modern datacenters are reinforcing the computational power and energy efficiency by assimilating field programmable gate arrays (FPGAs). The sustainability of this large-scale integration depends on enabling multi-tenant FPGAs. This requisite amplifies the importance of communication architecture and virtualization method with the required features in order to meet the high-end objective. Consequently, in the last decade, academia and industry proposed several virtualization techniques and hardware architectures for addressing resource management, scheduling, adoptability, segregation, scalability, performance-overhead, availability, programmability, time-to-market, security, and mainly, multitenancy. This paper provides an extensive survey covering three important aspects—discussion on non-standard terms used in existing literature, network-on-chip evaluation choices as a mean to explore the communication architecture, and virtualization methods under latest classification. The purpose is to emphasize the importance of choosing appropriate communication architecture, virtualization technique and standard language to evolve the multi-tenant FPGAs in datacenters. None of the previous surveys encapsulated these aspects in one writing. Open problems are indicated for scientific community as well.

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“…Like full bitstreams, partial bitstreams contain a header and a footer; these sections serve the same purposes as before. However, if the RESET AFTER RECONFIG property is set on the PR region, as is usually the case, CFG CLB frames precede the other configuration frames [24]. CFG CLB frames are mostly undocumented by Xilinx, but a comparison of different partial bitstreams reveals that the contents of this section of the bitstream differ for different PR regions [25].…”

Section: Partial Bitstream Generationmentioning

confidence: 99%

Maverick: A Stand-Alone CAD Flow for Partially Reconfigurable FPGA Modules

Glick

Grigg

Nelson

et al. 2019

2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)

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Circuit designs for field-programmable gate arrays (FPGAs) are typically compiled by FPGA vendor tools, such as Xilinx's Vivado Design Suite. In recent years, partial reconfiguration (PR) has emerged as a popular technique that allows portions of an FPGA to be dynamically reconfigured after the complete device has been configured with an initial bitstream. However, the nature of current FPGA vendor tools limits further innovation and possible usage models of PR. This thesis presentsMaverick, an open-source proof-of-concept computer-aided design (CAD) flow for generating reconfigurable modules (RMs) which target PR regions in FPGA designs. Maverick builds upon existing open source tools (Yosys [1], RapidSmith2 [2], and Project X-Ray [3]) to form an end-to-end compilation flow. After an initial static design and PR region are created with Xilinx's Vivado PR flow, Maverick can then compile and configure RMs onto that PR region-without the use of vendor tools. In addition, this work enables users to import and export RMs between Vivado and RapidSmith2.Furthermore, this thesis demonstrates Maverick compiling RMs on both a desktop computer and on the embedded PYNQ-Z1 board, which contains a Zynq 7020 system on chip (SoC). Maverick runs on the ARM processor embedded within the processing system (PS) of the Zynq device, generating partial bitstreams which can then be configured onto a PR region within the programmable logic (PL) fabric of the same Zynq device. This unique case, not possible with current vendor tools like Vivado, demonstrates the feasibility of a single-chip embedded system which can both compile HDL designs to bitstreams and then configure them onto its own programmable fabric.

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Preemptive Hardware Multitasking in ReconOS

Cited by 42 publications

References 8 publications

A Survey on FPGA Virtualization

A Survey on FPGA Virtualization

Revisiting the High-Performance Reconfigurable Computing for Future Datacenters

Maverick: A Stand-Alone CAD Flow for Partially Reconfigurable FPGA Modules

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