Present and future directions for multichip module technologies

Sudo, Takashi

doi:10.1109/4.375964

Cited by 11 publications

(5 citation statements)

References 12 publications

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“…The packaging of the core chips is shown in Table I. If the core chips are designed for , we can easily augment it to 1024 1024 by employing multichip module [16] technology. The number of the core distribution and concentration chips is 2048 each, and the number of the small distribution and concentration units is also 1024 each.…”

Section: Resultsmentioning

confidence: 99%

“…With dynamic logic [15], we require 113 transistors for each comparison element to run at a speed of 155 Mbit/s. To achieve the cell loss rate at 10 , we use , and then we need to construct 16 16 sorters (80 comparison elements/sorter) and 32 16 concentrating mergers (48 comparison elements/merger). If there are 512 input ports, then we need 32 sorters (289 280 transistors) and 31 concentrating mergers (168 144 transistors).…”

Section: B Core Chip Complexitymentioning

confidence: 99%

“…Since are independent, is the convolution of all 's. Then the generating function of is (16) where is the generating function of . We assume that is also i.i.d., and follows a probability mass function .…”

Section: Appendix Effective Offered Loadmentioning

confidence: 99%

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A large scalable ATM multicast switch

Law¹,

Leon-Garcia²

1997

IEEE J. Select. Areas Commun.

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This paper focuses on designing a large N 2 N high-performance broad-band ATM switch. Despite advances in architectural designs, practical switch dimensions continue to be severely limited by both the technological and physical constraints of packaging. Here, we focus on augmentation in a "single-switch" design: we provide ways to construct arbitrarily large switches out of modest-size components and retain overall delay/throughput performance. We propose a growable switch architecture based on several key principles: 1) the knockout principle exploits the statistical behavior of cell arrivals, and thereby reduces the interconnect complexity; 2) output queueing yields the best possible delay/throughput performance; 3) distributed control in routing (multicast) cells through the interconnect fabric without internal path conflicts; and 4) simple basic building blocks facilitate scalability. Other attractive features of the proposed architecture include: 1) intrinsic broadcast and multicast capabilities; 2) built-in priority sorting functionality; and 3) the guarantee of first-in, first-out cell sequence. To achieve 10 014 cell loss probability, only maximum size 32 2 16 basic building modules are required, and no crossover interconnects exist between modules in a three-dimensional configuration.

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Section: Resultsmentioning

confidence: 99%

Section: B Core Chip Complexitymentioning

confidence: 99%

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A large scalable ATM multicast switch

Law¹,

Leon-Garcia²

1997

IEEE J. Select. Areas Commun.

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“…However, it requires a special process like lamination and it's drilling. Multi-chip module (MCM) technology becomes another candidate [17]. Nevertheless, the quality of MCM-L integrated passives are relatively poor and limited to low frequencies [18] and may waste a large connection area because of wide line and separation width [19].…”

Section: Introductionmentioning

confidence: 99%

Wafer-Level Integration Technique of Surface Mount Devices on a Si-Wafer With Vibration Energy and Gravity Force

Sudou

Takao²,

Sawada³

et al. 2007

IEEE Trans. Comp. Packag. Technol.

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This paper reports about a novel wafer-level integration technique of discrete surface mount devices (SMDs). It enables wafer-level mounting of plural kinds of SMDs on a silicon (Si)-wafer using vibration and gravity force. Deep holes with 400-m depth are formed on the surface of a Si-wafer by deep reactive ion etching process after general integrated circuit process for positioning of SMDs. A non-conductive adhesive (CYTOP) are coated on the deep holes and it is used to fix the aligned SMDs. SMDs are distributed on a Si-wafer mounted on vibration generator, and then a vibration is applied. The SMDs migrate due to the reduced friction between the wafer surface, and they drop into the holes on the silicon wafer. The size of the holes has an appropriate clearance to the size of SMD. In order to align two or more kinds of SMDs, sizes of the deep holes on a Si-wafer are adjusted to the size of each SMD. SMDs with the largest size are dropped into the holes first, and then the secondary large SMDs are dropped into the holes with the corresponding size. SMDs are finally connected electrically by wire bonding at the final step. In the experiment, two different sizes of SMD were successfully mounted into all the holes on a Si-wafer automatically. This technology will be a wafer-level process technology which is very promising to integrate two or more kinds of discrete elements.Index Terms-Embedded passive integrated circuits (emPIC), passive integration, silicon integrated circuit (IC) technology.

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“…It is obvious in the future that reduction of power dissipation of the bus wiring will be very effective in the power reduction of a VLSI, since the bus is a group of wires in the VLSI. When multichip module (MCM) technology [3] is realized, data transmission between chips will be increased extensively.…”

Section: Introductionmentioning

confidence: 99%

Adaptive codebook encoding for low-power chip interface

Komatsu

Ikeda

Asada

2000

Electron. Comm. Jpn. Pt. II

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This paper proposes a method of adaptive codebook encoding to reduce the power dissipation of the chip interface of integrated circuits. To reduce the signal‐transition frequency, the minimum signal is transmitted, taking the difference of the input data code and the code in the codebook. The proposed adaptive codebook encoding has been successfully applied to random data and partial data in computer simulations. Prototype chips for the encode/decode circuit have been made, and their power dissipation has been examined. © 1999 Scripta Technica, Electron Comm Jpn Pt 2, 83(1): 17–23, 2000

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Present and future directions for multichip module technologies

Cited by 11 publications

References 12 publications

A large scalable ATM multicast switch

A large scalable ATM multicast switch

Wafer-Level Integration Technique of Surface Mount Devices on a Si-Wafer With Vibration Energy and Gravity Force

Adaptive codebook encoding for low-power chip interface

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