Principles of optimisation, modelling and testing of intelligent cyclic A/D converters

Principles of new method of optimisation, design and modelling of pipeline A/D converters

“…The architectures of the intelligent PADC and its particular stages are determined by a necessity to realise longbit operations and by the form of the sub-optimal codes computing algorithm [5][6][7][8]. General structures of IP ADC and its k-th stage, which realise a conversion according to the algorithm [5][6][7][8], are presented in Figs.…”

“…The approach allows to determine analytically the close-to-optimal, under given conditions, structure and values of the parameters of the converter which requires minimal heuristic corrections to guarantee maximal speed and accuracy of conversion under given permissible probability of saturation. Similar approach was applied to optimisation and design of the laboratory prototype of intelligent cyclic A/D converter (IC ADC) [6][7][8], realised in CMOS AMS 0.35 l technology, nowadays investigated.…”

“…First of all, this is a resignation from the common for conventional PADC method of the input signal codes computing in the form of a sum of shifted low-bit binary words delivered by sequential stages (see also [6][7][8]). In IP ADC, these codes are computed in each stage of conversion as long-bit binary words of fixed length N comp (N comp = 16 Ä 32-bits is the number of bits in binary words representing the codes of the sample computed in the digital part, and should be 3-5 bits greater than the required resolution of IP ADC).…”

“…The impossibility to set the gains to the greater values and increase SNR restricts possibilities to utilize entirely resources of the analogue and digital parts of PADC which decreases overall performance of the converters in comparison with the potentially available. Transition to long-bit codes computing removes this constraint [5][6][7][8].…”

“…In IP ADC, similarly as in IC ADC [6][7][8], potential overloading is excluded by setting the parameters of analogue elements and codes computing algorithm, in each stage, to the close-to-optimal values. Apart from obtaining the analytically grounded recommendations for optimal architecture and parameters of IP ADC, the proposed in the paper approach enables preliminary evaluation of expected performance of the converter.…”