Principles of Power Integrity for PDN Design:

Efficient Iterative Process Based on an Improved Genetic Algorithm for Decoupling Capacitor Placement at Board Level

“…In this work, the number of ports considered is Nports = 4. This extension of fcost to four (or in general Nports) ports allows the algorithm to choose the value and positioning of the decaps that minimize the input impedance only where is necessary, thus, improving the resilience of the PDN to the simultaneous switching noise (SSN) [8]. The new cost function is defined according to Equations (1-2): In Figure 1b, it is shown the flowchart of the improved GA, the object of this work, in which the new blocks of the binary coding/decoding, of the removal of the twin chromosomes, and of the iterative strategy are visible; they are discussed, in detail, in Section 2.2.…”

“…In this work, the number of ports considered is N ports = 4. This extension of f cost to four (or in general N ports ) ports allows the algorithm to choose the value and positioning of the decaps that minimize the input impedance only where is necessary, thus, improving the resilience of the PDN to the simultaneous switching noise (SSN) [8]. The new cost function is defined according to Equations (1)-(2):…”

“…In this scenario of miniaturized devices, the integrity of the digital signals (Signal Integrity, SI) is impaired by the quality (or even, in this case, integrity) of the electric power (Power Integrity, PI) associated with/given by the power/ground supply voltage at board level [8]. Modern approaches cannot disregard or ignore a correct and efficient design of the power delivery network (PDN) in order to decrease the transient noise caused by voltage droops, due to switching currents [8,9]. Several techniques have been proposed to improve the PI, based on Electromagnetic Band-gap (EBG) structures [10], among other techniques [11].…”

“…The goal of the PDN design is to achieve the input impedance seen by the power pins of the active devices (integrated circuits, IC, such as FPGA, DSP etc.) below the target impedance; with the latter being the ratio between the maximum noise on the DC supply voltage that can be tolerated by the active circuits, ∆V n , and the current I in drawn from the PDN by the transmitting devices [8]. Usually, the target impedance is flat over a wide range of frequency [6,15,17], leading to overdesign the PDN by adding more decaps than needed.…”

Decoupling Capacitors Placement at Board Level Adopting a Nature-Inspired Algorithm

“…Among the several causes that can lead to signal integrity (SI) problems, the power integrity (PI) related to the power/ground supply voltage at board level is one of the central requirements of modern design; having a power distribution network (PDN) defined by a high inductance or spending not enough time and effort on the PDN impedance design can cause severe PI issues [3]. Adopting decoupling capacitances (decaps) [4] is an effective solution in the optic of the reduction of transient noise caused by voltage droop due to the switching currents. A manual placement of decaps can lead to not optimal solution and can be time consuming; for these reasons, CAD tools and new algorithms [5][6][7][8] try to propose automatic procedures for the decaps arrangement.…”