Printed Electronics Based on Inorganic Semiconductors: From Processes and Materials to Devices

Abstract

Following the ever-expanding technological demands, printed electronics has shown palpable potential to create new and commercially viable technologies that will benefit from its unique characteristics, such as, large-area and wide range of substrate compatibility, conformability and low-cost. Through the last few decades, printed/solution-processed field-effect transistors (FETs) and circuits have witnessed immense research efforts, technological growth and increased commercial interests. Although printing of functional inks comprising organic semiconductors has already been initiated in early 1990s, gradually the attention, at least partially, has been shifted to various forms of inorganic semiconductors, starting from metal chalcogenides, oxides, carbon nanotubes and very recently to graphene and other 2D semiconductors. In this review, the entire domain of printable inorganic semiconductors is considered. In fact, thanks to the continuous development of materials/functional inks and novel design/printing strategies, the inorganic printed semiconductor-based circuits today have reached an operation frequency up to several hundreds of kilohertz with only a few nanosecond time delays at the individual FET/inverter levels; in this regard, often circuits based on hybrid material systems have been found to be advantageous. At the end, a comparison of relative successes of various printable inorganic semiconductor materials, the remaining challenges and the available future opportunities are summarized.

Progress Report on “From Printed Electrolyte‐Gated Metal‐Oxide Devices to Circuits”

“…[1][2][3][4][5][6] Currently, most of the devices in PE are based on organic materials; stateof-the-art printed field-effect transistors (FETs) consist of lithographically structured or printed electrodes and a printed organic semiconducting channel. [15][16][17][18][19][20][21][22] On the other hand, these devices cannot be operated at too high voltages (e.g., >5 V) since high bias stress could lead to chemical reactions and hence device instabilities. In general, OFETs have field-effect mobility values below 5 cm 2 V −1 s −1 and most applications based on OFETs require high supply voltages (≥5 V).…”

“…[15,23,24] Recent work by Xie et al includes a D Flip Flop realized in resistor-transistor logic (TR-logic), which is able to operate in the sub 2 V regime. [15,23,24] Recent work by Xie et al includes a D Flip Flop realized in resistor-transistor logic (TR-logic), which is able to operate in the sub 2 V regime.…”

“…The setup time of the D Flip Flop is less than 50 ms and the operation frequency is only around 5 Hz, however this example shows the potential of EGFETs for the use in complex circuits. [15,27,28] Single crystal oxide semiconductors, for instance, typically show the highest carrier mobility values, in the case of indium oxide specifically in the range of several 100 cm 2 V −1 s −1 . [26] The retention time of the DRAM cell is greater than 1 min when the write pulse is 20 ms long.…”

“…[25] A DRAM cell based on the same transistor technology as mentioned before which is able to operate at 1 V supply voltage is also presented in the literature. [15,29] Other favorable properties of these wide bandgap oxide semiconductors include stability in air over a wide temperature range, optical transperency, mechanical flexability, and their abilitiy to be easily processable in printing techniques. The high retention time is related to the fact that EGFETs have a high gate capacitance.…”

“…[26] The retention time of the DRAM cell is greater than 1 min when the write pulse is 20 ms long. [15,24,30,31] Promising circuits based on oxide semiconductors have already been successfully measured and show high stability under ambient conditions, lifetimes over several months as well as high performance. With the same EGFET, also a more complex circuit using 23 transistors with the functionality of an H-bridge driver is demonstrated at the supply voltage of 1 V. [11] In general, the circuit performance is a complex interplay between the DC performance of the in-build devices as well as the parasitic capacitances generated by interconnects as well as the single devices in the particular circuit layout.…”