Probabilistic Scheduling in High-Level Synthesis

Cheng, Jianyi; Wickerson, John; Constantinides, George A.

doi:10.1109/fccm51124.2021.00031

Cited by 4 publications

(4 citation statements)

References 25 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Synthesis means the time taken to emit RTL code. We measure the time taken for analysis using three approaches, simulation, discrete Petri net analysis [29] and analysis for continuous Petri net with immediate transitions. In the table, we observe the following:…”

Section: Resultsmentioning

confidence: 99%

See 1 more Smart Citation

Balancing Static Islands in Dynamically Scheduled Circuits Using Continuous Petri Nets

Cheng

Fraca

Wickerson

et al. 2023

IEEE Trans. Comput.

Self Cite

View full text Add to dashboard Cite

High-level synthesis (HLS) tools automatically transform a high-level program, for example in C/C++, into a low-level hardware description. A key challenge in HLS is scheduling, i.e. determining the start time of all the operations in the untimed program. A major shortcoming of existing approaches to scheduling -whether they are static (start times determined at compile-time), dynamic (start times determined at run-time), or a hybrid of both -is that the static analysis cannot efficiently explore the run-time hardware behaviours. Existing approaches either assume the timing behaviour in extreme cases, which can cause sub-optimal performance or larger area, or use simulation-based approaches, which take a long time to explore enough program traces. In this article, we propose an efficient approach using probabilistic analysis for HLS tools to efficiently explore the timing behaviour of scheduled hardware. We capture the performance of the hardware using Timed Continous Petri nets with immediate transitions, allowing us to leverage efficient Petri net analysis tools for making HLS decisions. We demonstrate the utility of our approach by using it to automatically estimate the hardware throughput for balancing the throughput for statically scheduled components (also known as static islands) computing in a dynamically scheduled circuit. Over a set of benchmarks, we show that our approach on average incurs a 2% overhead in area-delay product compared to optimal designs by exhaustive search.

show abstract

Section: Resultsmentioning

confidence: 99%

“…Our prior work [29] models dynamically scheduled hardware behaviour into discrete Petri nets, in particular stochastic Petri nets [14], which could lead to poor scalability. The complexity in hardware logic could lead to exponentially increasing number of states in the reachability graph.…”

Section: Module Selection In Hlsmentioning

confidence: 99%

Balancing Static Islands in Dynamically Scheduled Circuits Using Continuous Petri Nets

Cheng

Fraca

Wickerson

et al. 2023

IEEE Trans. Comput.

Self Cite

View full text Add to dashboard Cite

show abstract

“…We evaluate our work on a set of realistic benchmarks, comparing with the corresponding SS and DS designs in total circuit area and wall clock time. The IIs of static islands are automatically chosen by the II analyser in DASS [13]. We obtain the total clock cycles from Vivado XSIM simulator the area results from Post Synthesis report in Vivado.…”

Section: Methodsmentioning

confidence: 99%

“…This is extended to marked graphs in HLS tools like Dynamatic [32]. Cheng et al [13] propose a Petri net-based technique to optimise the initiation interval (II) of each SS component in a DS circuit. In pipelining, an II is defined as the number of clock cycles between the start times of two consecutive iterations.…”

Section: Module Selection and Optimisation In Hlsmentioning

confidence: 99%

Finding and Finessing Static Islands in Dynamically Scheduled Circuits

Cheng

Wickerson

Constantinides

2022

Proceedings of the 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

Self Cite

View full text Add to dashboard Cite

In high-level synthesis, scheduling is the process that determines the start time of each operation in hardware. A hardware design can be scheduled either at compile time (static), run time (dynamic), or both. Recent research has shown that combining dynamic and static scheduling can achieve high performance and small area. However, there is still a challenge to determine which part to schedule statically and which part dynamically. An inappropriate choice can lead to suboptimal design quality. This paper proposes a heuristicdriven approach to automatically determine 'static islands'i.e., code regions that are amenable for static scheduling. Over a set of benchmarks where our approach is applicable, we show that our tool can achieve on average a 3.8-fold reduction in area combined with a 13% performance boost through automatic identification and synthesis of static islands from fully dynamically scheduled circuits. The performance of the resulting hardware is close to optimum (as determined by an exhaustive enumeration of all possible static islands). CCS CONCEPTS• Hardware → High-level and register-transfer level synthesis; Logic synthesis; Modeling and parameter extraction.

show abstract

Efficient Design Space Exploration for Dynamic & Speculative High-Level Synthesis

Leothaud,

Gorius,

Rokicki

et al. 2024

2024 34th International Conference on Field-Programmable Logic and Applications (FPL)

View full text Add to dashboard Cite

High-Level Synthesis performs well for computeintensive loops with regular control but struggles to uncover parallelism in kernels with complex control-flow. Novel scheduling techniques based on dynamic scheduling and speculation have been proposed to address this issue. Although they outperform classical static scheduling techniques, they also come at a significant area overhead. Precisely determining where and by how much to apply these techniques remains an open problem, which we address in this work through an efficient exploration algorithm (combining pruning and search heuristics). We show that our approach can explore large solution spaces while producing efficient solutions.

show abstract

Probabilistic Scheduling in High-Level Synthesis

Cited by 4 publications

References 25 publications

Balancing Static Islands in Dynamically Scheduled Circuits Using Continuous Petri Nets

Balancing Static Islands in Dynamically Scheduled Circuits Using Continuous Petri Nets

Finding and Finessing Static Islands in Dynamically Scheduled Circuits

Efficient Design Space Exploration for Dynamic & Speculative High-Level Synthesis

Contact Info

Product

Resources

About