Probabilistic synaptic weighting in a reconfigurable network of VLSI integrate-and-fire neurons

Goldberg, David H.; Cauwenberghs, Gert; Andreou, Andreas G.

doi:10.1016/s0893-6080(01)00057-0

Cited by 110 publications

(86 citation statements)

References 23 publications

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“…In our probabilistic implementation, the input strength does not vary. Instead, w ij specifies the fraction of presynaptic neuron i's spikes that reach postsynaptic neuron j [8]. This approach eliminates the need for a digital-to-analog converter (assuming that the weights are stored digitally) and an analog multiplier.…”

Section: Hardware Elementsmentioning

confidence: 99%

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Silicon Neurons That Compute

Choudhary

Sloan

Fok

et al. 2012

Lecture Notes in Computer Science

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Abstract. We use neuromorphic chips to perform arbitrary mathematical computations for the first time. Static and dynamic computations are realized with heterogeneous spiking silicon neurons by programming their weighted connections. Using 4K neurons with 16M feed-forward or recurrent synaptic connections, formed by 256K local arbors, we communicate a scalar stimulus, quadratically transform its value, and compute its time integral. Our approach provides a promising alternative for extremely power-constrained embedded controllers, such as fully implantable neuroprosthetic decoders. Keywords: Neuromorphic chips, Silicon neurons, Probabilisitic synapses 1 Brain-Inspired Analog-Digital SystemsAnalog computation promises extreme energy-efficiency by operating close to the shot-noise limit [1]. By exploiting physical laws (e.g., conservation of charge for summation), a handful of analog devices is sufficient to perform computation. In contrast, digital computation relies on abstractions that require many more devices to achieve the same function (e.g., hundreds of transistors to add two 8-bit numbers). Furthermore, these abstractions break when noise exceeds a critical level, requiring enormous noise margins to avoid catastrophic failures. In contrast, analog degrades gracefully, allowing for operation at low noise margins, thereby saving power.However, robust and programmable computation using noisy analog circuits is challenging. Robust computation requires a distributed approach, but this is difficult because analog communication is susceptible to heterogeneity and noise. Programmable computation requires flexibility, but this is also difficult because analog computation exploits the underlying devices' fixed physical properties.In this paper, we realize robust and programmable mathematical computations with noisy and heterogeneous components using a framework inspired by the brain [2]. The brain uses graded dendritic potentials (cf. analog computation), all-or-none axonal spikes (cf. digital communication) and probabilistic synapses (cf. weighted connections). Our analog computational units are spiking silicon neurons [5]; our digital communication fabric is a packet-switched

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Section: Hardware Elementsmentioning

confidence: 99%

“…network [3]; and our weighted connections are packet-delivery probabilities [8]. While neuromorphic systems that combine some or all of these features of the brain have been built previously, they only performed specific computations.…”

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confidence: 99%

Silicon Neurons That Compute

Choudhary

Sloan

Fok

et al. 2012

Lecture Notes in Computer Science

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“…Chips that communicate using the AER communication protocol can be divided into senders with AER output only (e.g., silicon retinas [16], [17], or silicon cochleas [18]), receivers with AER input only [19], and transceiver chips, which are both senders and receivers [2], [7], [8]. Systems containing more than one AER sender chips can be assembled using off-chip arbitration.…”

Section: A Address Event Representation (Aer)mentioning

confidence: 99%

A Multichip Pulse-Based Neuromorphic Infrastructure and Its Application to a Model of Orientation Selectivity

Chicca

Whatley

Lichtsteiner

et al. 2007

IEEE Trans. Circuits Syst. I

122

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Abstract-The growing interest in pulse-mode processing by neural networks is encouraging the development of hardware implementations of massively parallel networks of integrate-and-fire neurons distributed over multiple chips. Address-event representation (AER) has long been considered a convenient transmission protocol for spike based neuromorphic devices. One missing, long-needed feature of AER-based systems is the ability to acquire data from complex neuromorphic systems and to stimulate them using suitable data. We have implemented a general-purpose solution in the form of a peripheral component interconnect (PCI) board (the PCI-AER board) supported by software. We describe the main characteristics of the PCI-AER board, and of the related supporting software. To show the functionality of the PCI-AER infrastructure we demonstrate a reconfigurable multichip neuromorphic system for feature selectivity which models orientation tuning properties of cortical neurons.

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“…In the brain, this is achieved by extensive connectivity between neural centers with distributed and parallel processing. In artificial neuromorphic systems, spikes can be rapidly transmitted to various locations using the address-event representation (AER) communication protocol [1][2][3], but relatively few solutions exist for real-time and large-scale processing of this spike-encoded sensory information (however, see [4][5][6][7][8][9][10][11] for some work in this direction).…”

Section: Introductionmentioning

confidence: 99%

A Real-Time Spike-Domain Sensory Information Processing System

Mallik

Vogelstein²,

Culurciello³

et al.

2005 IEEE International Symposium on Circuits and Systems

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We present an architecture for processing spike-based sensory information in real-time. The system is based on a re-configurable silicon array of general-purpose integrate-and-fire neurons (as opposed to application-specific circuits), which can emulate arbitrary cortical networks. A combined retinal/cortical network has been designed and tested with a neuromorphic silicon retina. Neural activity is communicated between chips at rates of up to 1,000,000 spikes/sec with a bit-parallel Address-Event Representation protocol. This work represents the first step in constructing an autonomous, continuous-time, biologically-plausible hierarchical model of visual information processing using large-scale arrays of identical silicon neurons.

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Probabilistic synaptic weighting in a reconfigurable network of VLSI integrate-and-fire neurons

Cited by 110 publications

References 23 publications

Silicon Neurons That Compute

Silicon Neurons That Compute

A Multichip Pulse-Based Neuromorphic Infrastructure and Its Application to a Model of Orientation Selectivity

A Real-Time Spike-Domain Sensory Information Processing System

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