Process and circuit design interlock for application-dependent scaling tradeoffs and optimization in the SoC era

Abstract

Several physical phenomena in highly scaled CMOS technology have now become first-order elements affecting the electrical behavior of transistor characteristics. Effects such as STI mechanical stress, direct tunneling in gate dielectrics, gate line-edge roughness, and others can have significant influence on device characteristics. This paper elaborates on these effects to exemplify the need for closer interaction between circuit design and process development teams in order to push out application-dependent scaling limits. The paper also highlights the need for further efforts in the areas of circuit-level device modeling.

Leakage current variability in nanometer technologies

“…In addition, line edge roughness (LER) due to lithographic and gate etching steps are becoming increasingly important as technology is scaled [6]. This is because the same roughness on the edge of a transistor becomes relatively more important as transistors are scaled down.…”

Nano‐CMOS Scaling Problems and Implications

“…ž Thinner source and drain diffusion increases RSD further, due to current crowding. ž Shallow trench isolation (STI) stress-induced mobility degradation is more pronounced, negatively affecting the NMOS transistor while the PMOS transistor improves slightly with STI stress [10,11].…”

“…Statistical dopant variation in the channels is difficult to model and affects the small-geometry transistors used in bit cells, which can least afford poor modeling [3]. Proximity effects and STI stress mobility degradation will be difficult to model since they are very layout dependent [10,11]. Some new tools have become available that offer some assistance in this area through layout extraction.…”