Leakage current variability in nanometer technologies

Anis, Mohab; Abu-Rahma, Mohamed H.

doi:10.1109/iwsoc.2005.78

Cited by 23 publications

(9 citation statements)

References 14 publications

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“…The nominal value of lint is 7.5 nm and its standard deviation is set to 3 nm based on the observation that effective transistor length has a 3σ value that is 10% of overall transistor length [1] …”

Section: Process Variationmentioning

confidence: 99%

Bitline PUF: Building Native Challenge-Response PUF Capability into Any SRAM

Holcomb

2014

Advanced Information Systems Engineering

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Abstract. Physical Unclonable Functions (PUFs) are specialized circuits with applications including key generation and challenge-response authentication. PUF properties such as low cost and resistance to invasive attacks make PUFs well-suited to embedded devices. Yet, given how infrequently the specialized capabilities of a PUF may be needed, the silicon area dedicated to it is largely idle. This inefficient resource usage is at odds with the cost minimization objective of embedded devices. Motivated by this inefficiency, we propose the Bitline PUF -a novel PUF that uses modified wordline drivers together with SRAM circuitry to enable challenge-response authentication. The number of challenges that can be applied to the Bitline PUF grows exponentially with the number of SRAM rows, and these challenges can be applied at any time without power cycling. This paper presents in detail the workings of the Bitline PUF, and shows that it achieves high throughput, low latency, and uniqueness across instances. Circuit simulations indicate that the Bitline PUF responses have a nominal bit-error-rate (BER) of 0.023 at 1.2 V supply and 27• C, and that BER does not exceed 0.076 when supply voltage is varied from 1.1 V to 1.3 V, or when temperature is varied from 0• C to 80 • C. Because the Bitline PUF leverages existing SRAM circuitry, its area overhead is only a single flip-flop and two logic gates per row of SRAM. The combination of high performance and low cost makes the Bitline PUF a promising candidate for commercial adoption and future research.

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Section: Process Variationmentioning

confidence: 99%

Bitline PUF: Building Native Challenge-Response PUF Capability into Any SRAM

Holcomb

2014

Advanced Information Systems Engineering

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“…Given any pair of components, Xi and Xj, we denote their correlation as either cor(Xi,Xj) or ρi,j. This Correlation is defined as ρ i,j = cov(Xi,Xj) / (σ i σ j ) (1) where σi and σj are the standard deviations of Xi and Xj.…”

Section: B Correlation Matrixmentioning

confidence: 99%

“…This increased variability in advanced CMOS technologies is playing an increased role in determining the total leakage of a chip. This has accentuated the need to statistically account for leakage variations during the design cycle [1]. Designing for worst case leakage may cause excessive guard-banding, resulting in lower performances.…”

Section: Introductionmentioning

confidence: 99%

Statistical leakage estimation in 32nm CMOS considering cells correlations

Joshi

Lombardot

Belleville

et al. 2012

2012 IEEE Faible Tension Faible Consommation

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“…Process variations are fluctuations around the desired value of design parameters introduced during chip device fabrication [4]. The process variations are, inter-die (die-to-die) and intra-die (within-die).…”

Section: Process Variationsmentioning

confidence: 99%

“…In today's designs, the yield is determined according to the operating frequency and the leakage power [4].…”

Section: Process Variationsmentioning

confidence: 99%