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Abstract

In this paper, a new technique fir the dual-thsliold voirage assignment with more eficiency is propowd In the proposed method. an assignment priority factor which quant$es the reduciion 3n the subthreshold current versus the &loy increase is &fined and utilized to select the proper gare(s). Using the fatw the gates with more decrease in the subfhreshold leakage current and less delay penal& aJier the assignment are given a higher priority This leads IO more high threshold volfage gates and. hence. a more staiic power reduction. The technique i s applied to the ISCASBS benchmarks achieving up 10 about 25% reduction in the subthreshold leakage compared to the conventional rechniqste.

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<p class="MsoNormal" style="text-align: left; margin: 0cm 0cm 0pt; layout-grid-mode: char;" align="left"><span class="text"><span style="font-family: ";Arial";,";sans-serif";; font-size: 9pt;">Rapid increase in transistor density and operating frequency has led to the increase in power densities, exhibiting itself as a high temperature profile. The high temperature spots over an FPGA impact the power, performance, and reliability of the chip, hence should be addressed during the design process. The logic block placement is targeted as the natural starting point to address the non-uniform thermal profile problem. The proposed placer simultaneously accounts for conventional placement objectives (routability and timing) while increases the temperature profile uniformity by optimizally spreading the power sources. As a measure of thermal uniformity in the simulation annealing core of the placer, a cost function is derived by adapting the concept of maximum entropy in a dual electrostatic charge model. The runtime complexity of this cost function is linear with respect to the number of used blocks, regardless of the size of the FPGA, and there is no need to perform the time-consuming thermal extractions. Results show an average of 73% and 51% reductions in the standard deviation and maximum gradient of temperature with less than 4% average wiring and delay penalty.</span></span><span style="font-family: ";Arial";,";sans-serif";; font-size: 9pt;"></span></p>