New dual-threshold voltage assignment technique for low-power digital circuits

Abstract

In this paper, a new technique fir the dual-thsliold voirage assignment with more eficiency is propowd In the proposed method. an assignment priority factor which quant$es the reduciion 3n the subthreshold current versus the &loy increase is &fined and utilized to select the proper gare(s). Using the fatw the gates with more decrease in the subfhreshold leakage current and less delay penal& aJier the assignment are given a higher priority This leads IO more high threshold volfage gates and. hence. a more staiic power reduction. The technique i s applied to the ISCASBS benchmarks achieving up 10 about 25% reduction in the subthreshold leakage compared to the conventional rechniqste.

NBTI-aware dual threshold voltage assignment for leakage power reduction

“…By assigning independent candidate gates to HTV at the same time (under timing constraints and circuit lifetime constraints), our approach is faster than the previous work [1] without any side effects. Our approach imposes no penalty on the circuit lifetime, while the previous work [1] may impose a penalty on the circuit lifetime.…”

“…Our approach achieves the same circuit lifetime as that of the original circuit. In fact, our approach is based on the framework introduced in a previous work [1]. However, compared with the previous work [1], our approach has the following three main features:…”

“…Therefore, leakage power reduction is an important topic in modern circuit design. Several techniques for leakage power reduction have been proposed, including power gating, input vector control, and dual threshold voltage (dual-Vth) assignment [1][2][3]. In the dual-Vth assignment technique, two types of logic libraries are used.…”

Analysis of Leakage Power Reduction Techniques for Low Power VLSI Design

“…In this technique, no additional transistors are required as in the case of multithreshold voltage technique. Reduction of static power is achieved while maintaining the same performance as single threshold voltage circuit [6], [7]. Care should be taken while designing, is that if all the transistors in the non-critical paths are assigned with HVT, non-critical path may become a new critical path with a larger path delay than the original one, deteriorating the speed of the circuit.…”

An Optimization Mechanism Intended for Static Power Reduction Using Dual‐VthTechnique

“…A dual-threshold algorithm that introduces a key priority factor for cells replacements has been proposed in [14]. In this work, the amount of subthreshold current reduction related to the increase of the cell delays determines the priority of a particular cell to be replaced in the circuit.…”