Leakage power dissipation plays a major role in the total power dissipation with the advancement in the technology. Reduction of leakage power is of top concern in the present trend of nanotechnology. Input Vector Control (IVC) is one of the approaches used for static power reduction during standby mode. Leakage in a circuit depends on input vector applied at primary inputs due to stacking effect. Minimum leakage vector (MLV) is the input vector to which a circuit can offer a minimum leakage for a given set of test inputs. This paper presents MLV for various test circuits using genetic algorithm. The algorithm is implemented in Verilog HDL to obtain MLV.Results explores that heuristic approaches can be considered as better algorithms in finding optimum solution. Another advantage found during simulation is that implementation of algorithm in HDL converges in less number of iterations with runtime savings compared to random search method.

Leakage power consumption plays a significant role in current CMOS technology. International Technology Roadmap for semiconductors reports that leakage power consumption dominates the total chip power consumption as technology advances to nano scale. Most of the battery operated applications such as cell phones, Laptops etc requires a longer battery life, which can be made possible by controlling leakage current flowing through the CMOS gate. This paper presents leakage current mechanisms and different leakage reduction techniques to reduce leakage power consumption. We propose a novel leakage reduction technique named "Galeorstack" which can achieve better leakage reduction by maintaining exact logic state than the other techniques discussed in this paper. The proposed technique has been verified and compared with the other techniques for NOR and EXOR logic circuits and implemented using standard cells of 90nm CMOS process from CADENCE TOOLS. GaleorStack technique would be the best choice to the designer for the low leakage and less delay while achieving exact logic state.

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