Verilog implementation of genetic algorithm for minimum leakage vector in input vector control approach

Abstract

Leakage power dissipation plays a major role in the total power dissipation with the advancement in the technology. Reduction of leakage power is of top concern in the present trend of nanotechnology. Input Vector Control (IVC) is one of the approaches used for static power reduction during standby mode. Leakage in a circuit depends on input vector applied at primary inputs due to stacking effect. Minimum leakage vector (MLV) is the input vector to which a circuit can offer a minimum leakage for a given set of test inputs. This paper presents MLV for various test circuits using genetic algorithm. The algorithm is implemented in Verilog HDL to obtain MLV.Results explores that heuristic approaches can be considered as better algorithms in finding optimum solution. Another advantage found during simulation is that implementation of algorithm in HDL converges in less number of iterations with runtime savings compared to random search method.

Particle Swarm Optimization Algorithm for Leakage Power Reduction in VLSI Circuits

“…Genetic algorithm is used by many authors to determine the minimum leakage vector as best solution [12] [13]. In the previous work of authors [11] genetic algorithm is used but implemented in Verilog HDL and comparison is performed with [14]. In this paper an attempt is made to implement Particle Swarm Optimization algorithm in the field of low power VLSI to search for MLV as an optimum solution.…”

“…Forcing the circuit to low leakage state to reduce leakage power is the basic concept in IVC [10]. Minimum leakage vector is the low leakage state determined among different test inputs applied to circuit [11]. Furthermore, IVC does not require any circuit modifications and depends on transistor stacking effect.…”

An Efficient Algorithm for Tracing Minimum Leakage Current Vector in Deep-Sub Micron Circuits

“…Boolean logic and probability used to trace the minimum leakage vector. Minimum leakage vector for test circuit can be produced using genetic algorithms [12]. Here algorithm is implemented using Verilog which saves run time and reduces leakage current in sleep mode.…”

Combined Gate Replacement and Transmission Gate Based Logic Insertion Algorithm for Leakage Optimization in VLSI Circuits

“…Abdoul Rjoub et al proposed Fast Input Vector Control Algorithm in [14] to search for MLV. Genetic Algorithm is used in [15,16] to find the minimum leakage state. Fig.3.…”