NBTI-aware dual threshold voltage assignment for leakage power reduction

Abstract

Dual threshold voltage (dual-Vth) assignment is recognized as a useful technique to reduce the leakage power. However, as the process technology shrinks to the deep sub-micron regime, the negative bias temperature instability (NBTI) effect becomes a serious concern. The NBTI effect may cause the degradation of threshold voltage over a period of months or years. Since previous dual-Vth assignment techniques do not consider the NBTI effect, they often decrease the circuit lifetime. In this paper, we propose an NBTI-aware dual-Vth assignment algorithm. Our objective is not only to reduce the leakage power but also to maintain the lifetime of the circuit. By assigning independent candidate gates to high threshold voltage (HTV) simultaneously, in each benchmark circuit, our approach can achieve a better result with a smaller CPU time. Experimental data consistently show that our approach works well in practice.

Assessment of Circuit Optimization Techniques Under NBTI

“…In a conventional dual threshold voltage assignment (DTVA) approach for leakage reduction, noncritical gates are assigned to high V th , leading to higher intrinsic delay and less time margin. Tu et al took NBTI into account when performing DTVA for leakage reduction [14]. Circuit lifetime is maintained by assigning more low-V th gates to decrease the intrinsic delay and leaving sufficient margin for NBTI degradation, while leakage is still reduced by assigning high-V th gates.…”