Thermal Driven Placement for Island-style MTCMOS FPGAs

Abstract

<p class="MsoNormal" style="text-align: left; margin: 0cm 0cm 0pt; layout-grid-mode: char;" align="left"><span class="text"><span style="font-family: ";Arial";,";sans-serif";; font-size: 9pt;">Rapid increase in transistor density and operating frequency has led to the increase in power densities, exhibiting itself as a high temperature profile. The high temperature spots over an FPGA impact the power, performance, and reliability of the chip, hence should be addressed during the design process. The logic block placement is targeted as the natural starting point to address the non-uniform thermal profile problem. The proposed placer simultaneously accounts for conventional placement objectives (routability and timing) while increases the temperature profile uniformity by optimizally spreading the power sources. As a measure of thermal uniformity in the simulation annealing core of the placer, a cost function is derived by adapting the concept of maximum entropy in a dual electrostatic charge model. The runtime complexity of this cost function is linear with respect to the number of used blocks, regardless of the size of the FPGA, and there is no need to perform the time-consuming thermal extractions. Results show an average of 73% and 51% reductions in the standard deviation and maximum gradient of temperature with less than 4% average wiring and delay penalty.</span></span><span style="font-family: ";Arial";,";sans-serif";; font-size: 9pt;"></span></p&gt

An Improved Diffusion Based Placement Algorithm for Reducing Interconnect Demand in Congested Regions of FPGAs

“…Our congestion driven placer strives to reduce the interconnect variations by evenly spreading the routing demand across the entire chip. We have adopted the same diffusion based placement technique as proposed in [14]. However, instead of using the technique for reducing high temperature spots, as done in [14], we have used the technique for reducing high-interconnect usage.…”

“…We have adopted the same diffusion based placement technique as proposed in [14]. However, instead of using the technique for reducing high temperature spots, as done in [14], we have used the technique for reducing high-interconnect usage. Moreover, unlike the work done in [10], size of FPGA is not increased.…”

“…Our placer uses a weighted common driver cost function similar to the one used in [14] except for the fact that the common driver weight in [14] corresponds to thermal cost extracted from the temperature profile of an FPGA while in our case it corresponds to the occupancy (defined in Section 3.1) of each CLB which we call the congestion cost.…”

“…In this work, we have implemented two new techniques for the better selection of CLBs, which show much better results compared to our previous fixed approach, while the results for metrics like critical delay and run-time of algorithm which were not reported in [13] are also included. Otherwise, there is no published work in FPGA domain which utilizes diffusion except [14] which utilizes diffusion based placement solution for reducing high temperature spots over an FPGA chip.…”

“…Jaffari and Anis [14] applied the concept of diffusion to address the uneven heat distribution problem in an FPGA by targeting thermal uniformity as the main objective function. The proposed placer tool uses a simulated annealing engine with a weighted common driver cost function to account for the issues of wirelength and performance requirements.…”